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2020-03-12Revert "arm64: dts: sdm845: add IPA information"Alex Elder
This reverts commit 9cc5ae125f0eaee471bc87fb5cbf29385fd9272a. This commit: b303f9f0050b arm64: dts: sdm845: Redefine interconnect provider DT nodes found in the Qualcomm for-next tree removes/redefines the interconnect provider node(s) used for IPA. I'm not sure whether it technically conflicts with the IPA change to "sdm845.dtsi" in for-next, but it renders it broken. Revert this commit in the for-next tree, with the plan to incorporate it into the Qualcomm tree instead. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-08arm64: dts: sdm845: add IPA informationAlex Elder
Add IPA-related nodes and definitions to "sdm845.dtsi". Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-02-08Merge tag 'armsoc-drivers' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms: - Nvidia: Fuse support for Tegra194, continued memory controller pieces for Tegra30 - NXP/FSL: Refactorings of QuickEngine drivers to support ARM/ARM64/PPC - NXP/FSL: i.MX8MP SoC driver pieces - TI Keystone: ring accelerator driver - Qualcomm: SCM driver cleanup/refactoring + support for new SoCs. - Xilinx ZynqMP: feature checking interface for firmware. Mailbox communication for power management - Overall support patch set for cpuidle on more complex hierarchies (PSCI-based) and misc cleanups, refactorings of Marvell, TI, other platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (166 commits) drivers: soc: xilinx: Use mailbox IPI callback dt-bindings: power: reset: xilinx: Add bindings for ipi mailbox drivers: soc: ti: knav_qmss_queue: Pass lockdep expression to RCU lists MAINTAINERS: Add brcmstb PCIe controller entry soc/tegra: fuse: Unmap registers once they are not needed anymore soc/tegra: fuse: Correct straps' address for older Tegra124 device trees soc/tegra: fuse: Warn if straps are not ready soc/tegra: fuse: Cache values of straps and Chip ID registers memory: tegra30-emc: Correct error message for timed out auto calibration memory: tegra30-emc: Firm up hardware programming sequence memory: tegra30-emc: Firm up suspend/resume sequence soc/tegra: regulators: Do nothing if voltage is unchanged memory: tegra: Correct reset value of xusb_hostr soc/tegra: fuse: Add APB DMA dependency for Tegra20 bus: tegra-aconnect: Remove PM_CLK dependency dt-bindings: mediatek: add MT6765 power dt-bindings soc: mediatek: cmdq: delete not used define memory: tegra: Add support for the Tegra194 memory controller memory: tegra: Only include support for enabled SoCs memory: tegra: Support DVFS on Tegra186 and later ...
2020-01-13arm64: dts: qcom: sdm845: move gpu zap nodes to per-device dtsRob Clark
We want to specify per-device firmware-name, so move the zap node into the .dts file for individual boards/devices. This lets us get rid of the /delete-node/ for cheza, which does not use zap. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200112195405.1132288-5-robdclark@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-13arm64: dts: qcom: sm8150: Hard code rpmhpd constantsBjorn Andersson
I missed the fact that these constants was not yet available, so hard code their values in the dts to make the branch compile on its own. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07arm64: dts: apq8096-db820c: Fix VDD core voltageLoic Poulain
APQ8096 has its VDD APC (Power for quad Kryo applications microprocessors) powered by PM8996 PMIC S9, S10, S11 tri-phase regulators (gang). The bootloader may have configured these regulators with non sustainable default values, leading to sporadic hangs under CPU stress tests (cpufreq-bench). Ideally we should enable voltage scaling along with frequency scaling, but for now just set the regulator gang value to a sane voltage, capable of supporting highest frequencies (turbo). Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Link: https://lore.kernel.org/r/1578401755-26211-1-git-send-email-loic.poulain@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07arm64: dts: qcom: qcs404-evb: Set vdd_apc regulator in high power modeNiklas Cassel
vdd_apc is the regulator that supplies the main CPU cluster. At sudden CPU load changes, we have noticed invalid page faults on addresses with all bits shifted, as well as on addresses with individual bits flipped. By putting the vdd_apc regulator in high power mode, the voltage drops during sudden load changes will be less severe, and we have not been able to reproduce the invalid page faults with the regulator in this mode. Fixes: 8faea8edbb35 ("arm64: dts: qcom: qcs404-evb: add spmi regulators") Cc: stable@vger.kernel.org Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20191014120920.12691-1-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07arm64: dts: qcom: msm8998-mtp: Add alias for blsp1_uart3Bjorn Andersson
The msm_serial driver has a predefined set of uart ports defined, which is allocated either by reading aliases or if no match is found a simple counter, starting at index 0. But there's no logic in place to prevent these two allocation mechanism from colliding. As a result either none or all of the active msm_serial instances must be listed as aliases. Define blsp1_uart3 as "serial1" to mitigate this problem. Fixes: 4cffb9f2c700 ("arm64: dts: qcom: msm8998-mtp: Enable bluetooth") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lore.kernel.org/r/20191119011823.379100-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-06arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS ↵Rajeshwari
in SC7180 Added critical interrupt support in TSENS node and cooling maps in Thermal-zones node. Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Rajeshwari <rkambl@codeaurora.org> Link: https://lore.kernel.org/r/1578317369-16045-2-git-send-email-rkambl@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-06arm64: dts: qcom: msm8996: Fix venus iommu nodename errorStanimir Varbanov
Fix the following error/warn seen with make dtbs_check arm,smmu-venus@d40000: $nodename:0: 'arm,smmu-venus@d40000' does not match '^iommu@[0-9a-f]*' arm,smmu-venus@d40000: clock-names:0: 'bus' was expected arm,smmu-venus@d40000: clock-names:1: 'iface' was expected by rename nodename to "iommu". Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Link: https://lore.kernel.org/r/20200106102305.27059-1-stanimir.varbanov@linaro.org [bjorn: Added padding of address to 8 digits] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-05arm64: dts: qcom: sdm845: add the ufs resetVinod Koul
Add the core UFS reset for sdm845 Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200106070826.147064-4-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-05arm64: dts: qcom: sm8150: Fix UFS phy register sizeVinod Koul
UFS phy register space size is 0x1c0. so update it Reported-by: Can Guo <cang@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200106070826.147064-3-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-05arm64: dts: qcom: sm8150-mtp: Add UFS gpio resetVinod Koul
Add the reset-gpio for UFS for sm8150-mtp. Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200106070826.147064-2-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04arm64: dts: qcom: qcs404: Add CPR and populate OPP tableNiklas Cassel
Add CPR and populate OPP table. Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20191129213917.1301110-4-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04arm64: dts: qcom: qcs404: Add DVFS supportJorge Ramirez-Ortiz
Support dynamic voltage and frequency scaling on qcs404. CPUFreq will soon be superseded by Core Power Reduction (CPR, a form of Adaptive Voltage Scaling found on some Qualcomm SoCs like the qcs404). Due to the CPR upstreaming already being in progress - and some commits already merged - the following commit will need to be reverted to enable CPUFreq support Author: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Date: Thu Jul 25 12:41:36 2019 +0200 cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191125142511.681149-5-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04arm64: dts: qcom: qcs404: Add the clocks for APCS mux/dividerJorge Ramirez-Ortiz
Specify the clocks that feed the APCS mux/divider instead of using default hardcoded values in the source code. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191125142511.681149-4-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04arm64: dts: qcom: qcs404: Add HFPLL nodeJorge Ramirez-Ortiz
The high frequency pll functionality is required to enable CPU frequency scaling operation. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191125142511.681149-3-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/dividerJorge Ramirez-Ortiz
Specify the clocks that feed the APCS mux/divider instead of using default hardcoded values in the source code. The driver still supports the previous bindings; however with this update it we allow the msm8916 to access the parent clock names required by the driver operation using the device tree node. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191125142511.681149-2-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04arm64: dts: qcom: sc7180: Add rpmh power-domain nodeSibi Sankar
Add the DT node for the rpmhpd power controller on SC7180 SoCs. Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20191220064823.6115-3-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-03arm64: dts: pm8004: Add SPMI regulator and add phandles to lsidsAngeloGioacchino Del Regno
Add the SPMI regulator node in the PM8004 LSID5 (as there is where it resides basically 99% of the times) and set the nodes to be disabled by default, as not all boards have both or one of the lsids specified in this generic pm8004 DT. While at it, also add nice phandles to the lsids specified in this DT to allow configuration in specific board dts in a more human readable fashion. Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com> Link: https://lore.kernel.org/r/20191031111645.34777-3-kholk11@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-02arm64: dts: Convert to the hierarchical CPU topology layout for MSM8916Ulf Hansson
To enable the OS to better support PSCI OS initiated CPU suspend mode, let's convert from the flattened layout to the hierarchical layout. In the hierarchical layout, let's create a power domain provider per CPU and describe the idle states for each CPU inside the power domain provider node. To group the CPUs into a cluster, let's add another power domain provider and make it act as the master domain. Note that, the CPU's idle states remains compatible with "arm,idle-state", while the cluster's idle state becomes compatible with "domain-idle-state". Co-developed-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
2019-12-28arm64: dts: msm8998: thermal: Add critical interrupt supportAmit Kucheria
Register critical interrupts for each of the two tsens controllers Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Link: https://lore.kernel.org/r/3ef309a98ca6445c1982ec3ff1a70db39b18f415.1575349416.git.amit.kucheria@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-28arm64: dts: msm8996: thermal: Add critical interrupt supportAmit Kucheria
Register critical interrupts for each of the two tsens controllers Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Link: https://lore.kernel.org/r/53d8f7b922ec889ed11380896c2a367ae0998db2.1575349416.git.amit.kucheria@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: db845c: Move remoteproc firmware to sdm845Bjorn Andersson
The redistributable firmware should work on any engineering device, so lets push this to qcom/sdm845, rather than qcom/db845c. Also specify the path for the modem firmware. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191113203951.3704428-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: msm8996: Introduce IFC6640Bjorn Andersson
Introduce a base dts for the Inforce 6640 Single Board Computer. This initial commit boots to console on the uart and provides UFS and SD card storage support. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: db820c: Use regulator names from schematicsBjorn Andersson
Update the regulator names in db820c.dtsi to use the names from the schematics, instead of the made up genric names. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: msm8996: Sort all nodes in msm8996.dtsiBjorn Andersson
Sort all the nodes by unit address, then name. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: msm8996: Pad addressesBjorn Andersson
Pad all addresses in msm8996.dtsi to 8 digits, in order to make it easier to ensure ordering when adding new nodes. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: db820c: Remove pin specific filesBjorn Andersson
Rather than scattering pinctrl definitions in various files, merge the nodes into db820c.dtsi to make it easier to navigate. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: db820c: Sort all nodesBjorn Andersson
Sort all nodes in db820c.dtsi based on address, then name. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: db820c: Group root nodesBjorn Andersson
Prior refactoring have left a few root nodes scattered throughout db820c.dtsi, group these at the top of the file. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: msm8996: Move regulators to db820cBjorn Andersson
As the definition of available PMICs and the names of their outputs are board specifc move this to db820c.dtsi Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: msm8996: Move regulator consumers to db820cBjorn Andersson
Supplies for the various components in the SoC depends on board layout, so move the supply definitions to db820c.dtsi instead of carrying them in the platform dtsi. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: msm8996: Use node references in db820cBjorn Andersson
Instead of mimicing the structure of the platform, reference nodes by their label in apq8096-db820c.dtsi. Add labels in msm8996.dtsi where necessary. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: db820c: Move non-soc entries out of /socBjorn Andersson
The USB id pins and wlan regulator are not platform devices, so move them out of /soc Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-21arm64: dts: qcom: db845c: Enable ath10k 8bit host-cap quirkBjorn Andersson
The WiFi firmware used on db845c implements the 8bit host-capability message, so enable the quirk for this. Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191113232245.4039932-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-21arm64: dts: qcom: sdm845: Rename gic-its node to msi-controllerDouglas Anderson
This is just like commit ac00546a6780 ("arm64: dts: qcom: sc7180: Rename gic-its node to msi-controller") but for sdm845. This fixes all arm64/qcom device trees that I could find. Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191216222021.1.I684f124a05a1c3f0b113c8d06d5f9da5d69b801e@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-20arm64: dts: qcom: msm8998: Add ADSP, MPSS and SLPI nodesSibi Sankar
This patch adds ADSP, MPSS and SLPI nodes for MSM8998 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20191218132217.28141-6-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-20arm64: dts: qcom: msm8998: Update reserved memory mapSibi Sankar
Update existing and add missing regions to the reserved memory map, as described in version 7.1 Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20191218132217.28141-5-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-19arm64: dts: qcom: sc7180: Add remoteproc enablersSibi Sankar
Add scm, smem, smp2p, aoss-qmp, aoss-cc and pdc-global device nodes to SC7180 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20191218143332.29107-1-sibis@codeaurora.org [bjorn: Updated subject] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-19arm64: dts: qcom: sm8150: Add cpufreq HW device nodeSibi Sankar
Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores on SM8150 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20191219120633.20723-1-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-19arm64: dts: qcom: qcs404: Update the compatible for watchdog timerSai Prakash Ranjan
Update the compatible for QCS404 watchdog timer with proper SoC specific compatible. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/757995875cc12d3f5a8f5fd5659b04653950970a.1576211720.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-18arm64: dts: qcom: sc7180: Fix I2C/UART numbers 2, 4, 7, and 9Douglas Anderson
Commit f4a73f5e2633 ("pinctrl: qcom: sc7180: Add new qup functions") has landed which means that we absolutely need to use the proper names for the pinmuxing for I2C/UART numbers 2, 4, 7, and 9. Let's do it. For reference: - If you get only one of this commit and the pinctrl commit then none of I2C/UART 2, 4, 7, and 9 will work. - If you get neither of these commits then I2C 2, 4, 7, and 9 will work but not UART. ...but despite the above it should be fine for this commit to land in the Qualcomm tree because sc7180.dtsi only exists there (it hasn't made it to mainline). Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org> Fixes: ba3fc6496366 ("arm64: dts: sc7180: Add qupv3_0 and qupv3_1") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191217130352.1.Id8562de45e8441cac34699047e25e7424281e9d4@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-17arm64: dts: msm8998-clamshell: Add pm8005_s1 regulatorJeffrey Hugo
The pm8005_s1 is VDD_GFX, and needs to be on to enable the GPU. This should be hooked up to the GPU CPR, but we don't have support for that yet, so until then, just turn on the regulator and keep it on so that we can focus on basic GPU bringup. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lore.kernel.org/r/20191217170249.5280-1-jeffrey.l.hugo@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-17arm64: dts: qcom: sc7180: Add wakeup parent for TLMMMaulik Shah
Specify wakeup parent irqchip for sc7180 TLMM. Reviewed-by: Lina Iyer <ilina@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Cc: devicetree@vger.kernel.org Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Link: https://lore.kernel.org/r/1572419178-5750-3-git-send-email-mkshah@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-17arm64: dts: qcom: sm8150: Add ADSP, CDSP, MPSS and SLPI remoteprocsSibi Sankar
Add ADSP, CDSP, MPSS and SLPI device tree nodes for SM8150 SoC. Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20191217092503.10699-1-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-17arm64: dts: qcom: sc7180: Fix node orderMatthias Kaehlcke
The SC7180 device tree nodes should be ordered by address. Re-shuffle some nodes which currently don't follow this convention. Since we are already moving it add a missing leading zero to the address in the 'reg' property of the 'interrupt-controller@b220000' node. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191212170824.v2.1.I55198466344789267ed1eb5ec555fd890c9fc6e1@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-17arm64: dts: qcom: msm8998: Fixup uart3 gpio config for bluetoothJeffrey Hugo
It turns out that the wcn3990 can float the gpio lines during bootup, etc which will result in the uart core thinking there is incoming data. This results in the bluetooth stack getting garbage. By applying a bias to match what wcn3990 would drive, the issue is corrected. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lore.kernel.org/r/20191021161921.31825-1-jeffrey.l.hugo@gmail.com [bjorn: Moved board specific pinctrl states to the end] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-16arm64: dts: qcom: sdm845-cheza: Add cr50 spi nodeStephen Boyd
Add the cr50 device to the spi controller it is attached to. This enables /dev/tpm0 and some login things on Cheza. Reviewed-by: Douglas Anderson <dianders@chromium.org> Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20191216234204.190769-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-16arm64: dts: qcom: sm8150: Add ADSP, CDSP, MPSS and SLPI smp2pSibi Sankar
Add the SMP2P nodes for the remoteproc states for ADSP, CDSP, MPSS and SLPI remoteprocs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/0101016e80793dfa-9d0f6e93-01db-4c95-a226-d64bb50238cb-000000@us-west-2.amazonses.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
generated by cgit (git 2.34.1) at 2024-06-07 07:22:06 +0000