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2023-05-08arm64: dts: renesas: r9a07g044: Add MTU3a nodeBiju Das
Add MTU3a node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230417090159.191346-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08arm64: dts: renesas: rzg2lc-smarc: Enable CRU, CSI supportLad Prabhakar
Enable CRU, CSI on RZ/G2LC SMARC EVK and tie the CSI to the OV5645 sensor using Device Tree overlay. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230413114016.16068-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08arm64: dts: renesas: rzv2l-smarc: Enable CRU, CSI supportLad Prabhakar
Enable CRU, CSI on RZ/V2L SMARC EVK and tie the CSI to the OV5645 sensor using Device Tree overlay. RZ/G2L SMARC EVK and RZ/V2L SMARC EVK have the same connections for connecting the CSI to OV5645 sensor so just reuse the existing r9a07g044l2-smarc-cru-csi-ov5645.dtso and create a symbolic link to this file for RZ/V2L SMARC EVK. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230412185608.64628-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08arm64: dts: renesas: r9a07g054: Add CSI and CRU nodesLad Prabhakar
Add CSI and CRU nodes to r9a07g054 (RZ/V2L) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230412185608.64628-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08arm64: dts: renesas: rzg2lc-smarc: Link DSI with ADV7535Biju Das
Enable DSI and ADV7535 and link DSI with ADV7535 on RZ/G2LC SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230411100346.299768-9-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08arm64: dts: renesas: rzg2l-smarc: Link DSI with ADV7535Biju Das
Enable DSI and ADV7535 and link DSI with ADV7535 on RZ/G2L SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230411100346.299768-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08arm64: dts: renesas: r9a07g054: Add DSI nodeBiju Das
Add DSI node to RZ/V2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230411100346.299768-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08arm64: dts: renesas: r9a07g044: Add DSI nodeBiju Das
Add DSI node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230411100346.299768-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08arm64: dts: renesas: r9a07g054: Add vspd nodeBiju Das
Add vspd node to RZ/V2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230411100346.299768-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08arm64: dts: renesas: r9a07g044: Add vspd nodeBiju Das
Add vspd node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230411100346.299768-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08arm64: dts: renesas: r9a07g054: Add fcpvd nodeBiju Das
Add fcpvd node to RZ/V2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230411100346.299768-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08arm64: dts: renesas: r9a07g044: Add fcpvd nodeBiju Das
Add fcpvd node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230411100346.299768-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-04-04arm64: dts: renesas: r8a779a0: Revise renesas,ipmmu-mainGeert Uytterhoeven
Since IMSSTR register was undocumented on the latest datasheet and dt-bindings of renesas,ipmmu-vmsa was updated about the renesas,ipmmu-main property, revise the property on each cache IPMMU node. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/ed4c21150e42dd23412a8f4af7976f81edc1c9c2.1680592069.git.geert+renesas@glider.be
2023-04-04arm64: dts: renesas: falcon-csi-dsi: Set bus-type for MAX96712Niklas Söderlund
Specify the bus-type property for all three connected MAX96712. The default behavior when parsing a node without this property is to default to D-PHY. Making this explicit plays it safe and future proofs things as the default parsing comes from the V4L2 core and not the driver itself. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230331141431.3820311-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-04-04arm64: dts: renesas: r8a779g0: Add iommus to MMC nodeYoshihiro Shimoda
Add iommus property to the MMC node for r8a779g0. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230123013448.1250991-6-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-04-04arm64: dts: renesas: r8a779g0: Add iommus to DMAC nodesYoshihiro Shimoda
Add iommus properties to the DMAC nodes for r8a779g0. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230123013448.1250991-5-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-04-04arm64: dts: renesas: r8a779g0: Add IPMMU nodesYoshihiro Shimoda
Add IPMMU nodes for r8a779g0. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20230123013448.1250991-4-yoshihiro.shimoda.uh@renesas.com [geert: Drop indices from renesas,ipmmu-main properties] [geert: s/hsc/hc/, s/vc0/vc/] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-04-04arm64: dts: renesas: r8a779f0: Revise renesas,ipmmu-mainYoshihiro Shimoda
Since IMSSTR register was undocumented on the latest datasheet and dt-bindings of renesas,ipmmu-vmsa was updated about the renesas,ipmmu-main property, revise the property on each cache IPMMU node. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20230123013448.1250991-2-yoshihiro.shimoda.uh@renesas.com [geert: Drop indices from renesas,ipmmu-main properties] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-30arm64: dts: renesas: rzg2l-smarc: Enable CRU, CSI supportLad Prabhakar
Enable CRU, CSI on RZ/G2L SMARC EVK and tie the CSI to OV5645 sensor using Device Tree overlay. rz-smarc-cru-csi-ov5645.dtsi is created so that RZ/G2L alike EVKs can make use of it. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230322125648.24948-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-30arm64: dts: renesas: r9a07g044: Add CSI and CRU nodesLad Prabhakar
Add CSI and CRU nodes r9a07g044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230322125648.24948-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-30arm64: dts: renesas: r9a07g044: Enable SCI0 using DT overlayBiju Das
Enable sci0 node using dt overlay and disable can{0,1}-stb-hog nodes in DT overlay as its pins are shared with sci0 pins. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230321114753.75038-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-30arm64: dts: renesas: rzg2l: Add clock-names and reset-names to DMAC nodesBiju Das
Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and RZ/Five DMAC nodes. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230315064726.22739-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-16arm64: dts: renesas: r8a779a0: Update CAN-FD to R-Car Gen4 compatible valueGeert Uytterhoeven
Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence update the compatible property in the CAN-FD device node to include the family-specific compatible value for R-Car Gen4. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9823058fa57156e88a084a4a99fc8525af1686ff.1678705389.git.geert+renesas@glider.be
2023-03-16arm64: dts: renesas: ulcb: Add I2C EEPROM for PMICGeert Uytterhoeven
Add a device node for the I2C EEPROM which serves as external storage for the PMIC setup. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/b52c6c21a94aa7320ac0c900f7023a5dfca76a29.1678375464.git.geert+renesas@glider.be
2023-03-16arm64: dts: renesas: condor: Add I2C EEPROM for PMICGeert Uytterhoeven
Add a device node for the I2C EEPROM which serves as external storage for the PMIC setup. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/84971f48eca0b696f592a922268af8c150d9bae3.1678375464.git.geert+renesas@glider.be
2023-03-10arm64: dts: renesas: Remove R-Car H3 ES1.* devicetreesWolfram Sang
R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support and disable booting for this SoC. Public users only have ES2 onwards. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230307105645.5285-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-10arm64: dts: renesas: white-hawk: Add R-Car Sound supportKuninori Morimoto
Add R-Car Sound support for the White Hawk board with the ARD-AUDIO-DA7212 external audio board, using a DT overlay. Signed-off-by: Linh Phung <linh.phung.jy@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87o7p5l9t7.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-10arm64: dts: renesas: r8a779g0: R-Car Sound supportKuninori Morimoto
Add sound support for R-Car V4H. Signed-off-by: Linh Phung <linh.phung.jy@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87pm9ll9ue.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-10arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channelsLad Prabhakar
From R01UH0968EJ0100 Rev.1.00 HW manual the interrupt numbers for SSI channels have been updated, SPI 329 - SSIF0 is now marked as reserved SPI 333 - SSIF1 is now marked as reserved SPI 335 - SSIF2 is now marked as reserved SPI 336 - SSIF2 is now marked as reserved SPI 341 - SSIF3 is now marked as reserved This patch drops the above IRQs from SoC DTSI. Fixes: 559f2b0708c70 ("arm64: dts: renesas: r9a07g043: Add SSI{1,2,3} nodes and fillup the SSI0 stub node") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230217185225.43310-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-10arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channelsLad Prabhakar
From R01UH0936EJ0120 Rev.1.20 HW manual the interrupt numbers for SSI channels have been updated, SPI 329 - SSIF0 is now marked as reserved SPI 333 - SSIF1 is now marked as reserved SPI 335 - SSIF2 is now marked as reserved SPI 336 - SSIF2 is now marked as reserved SPI 341 - SSIF3 is now marked as reserved This patch drops the above IRQs from SoC DTSI. Fixes: cd0339ec25895c0b ("arm64: dts: renesas: r9a07g054: Add SSI{1,2,3} nodes and fillup the SSI0 stub node") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230217185225.43310-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-10arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channelsLad Prabhakar
From R01UH0914EJ0120 Rev.1.20 HW manual the interrupt numbers for SSI channels have been updated, SPI 329 - SSIF0 is now marked as reserved SPI 333 - SSIF1 is now marked as reserved SPI 335 - SSIF2 is now marked as reserved SPI 336 - SSIF2 is now marked as reserved SPI 341 - SSIF3 is now marked as reserved This patch drops the above IRQs from SoC DTSI. Fixes: 92a341315afc9 ("arm64: dts: renesas: r9a07g044: Add SSI support") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230217185225.43310-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-10arm64: dts: renesas: r8a774c0: Remove bogus voltages from OPP tableGeert Uytterhoeven
According to the RZ/G Series, 2nd Generation Hardware User’s Manual Rev. 1.11, the System CPU cores on RZ/G2E do not have their own power supply, but use the common internal power supply (typical 1.03V). Hence remove the "opp-microvolt" properties from the Operating Performance Points table. They are optional, and unused, when none of the CPU nodes is tied to a regulator using the "cpu-supply" property. Fixes: 231d8908a66fa98f ("arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/8348e18a011ded94e35919cd8e17c0be1f9acf2f.1676560856.git.geert+renesas@glider.be
2023-03-10arm64: dts: renesas: r8a77990: Remove bogus voltages from OPP tableGeert Uytterhoeven
According to the R-Car Series, 3rd Generation Hardware User’s Manual Rev. 2.30, the System CPU cores on R-Car E3 do not have their own power supply, but use the common internal power supply (typical 1.03V). Hence remove the "opp-microvolt" properties from the Operating Performance Points table. They are optional, and unused, when none of the CPU nodes is tied to a regulator using the "cpu-supply" property. Fixes: dd7188eb4ed128dc ("arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9232578d9d395d529f64db3333a371e31327f459.1676560856.git.geert+renesas@glider.be
2023-03-10arm64: dts: renesas: r9a07g054: Add Cortex-A55 PMU nodeLad Prabhakar
Enable the performance monitor unit for the Cortex-A55 cores on the RZ/V2L (r9a07g054) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230206001300.28937-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06arm64: dts: renesas: white-hawk-csi-dsi: Add and connect MAX96712Niklas Söderlund
The sub-board contains two MAX96712 connected to the main-board using I2C and CSI-2, record the connections. Also enable all nodes (VIN, CSI-2 and ISP) that are part of the downstream video capture pipeline. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230211150012.3824154-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06arm64: dts: renesas: r8a779g0: Add and connect all CSI-2, ISP and VIN nodesNiklas Söderlund
The V4H have 16 VIN, 2 CSI-2 and 2 ISP nodes that interact with each other for video capture. Add all nodes and record how they are interconnected. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230211150012.3824154-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06arm64: dts: renesas: r8a779f0: Use proper labels for thermal zonesWolfram Sang
The documentation provides information about the placement of the zones, so that can be used for more descriptive labels. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230209200735.3882-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06arm64: dts: renesas: r8a779g0: Add thermal nodesGeert Uytterhoeven
Add device nodes for the Thermal Sensor/Chip Internal Voltage Monitor/Core Voltage Monitor (THS/CIVM/CVM) and the various thermal zones on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/b92a1a28afb9f75f24f0137af9f77e95d7ebaec3.1675959327.git.geert+renesas@glider.be
2023-03-06arm64: dts: renesas: rzv2mevk2: Add uart0 pinsBiju Das
Add uart0 pins in pinctrl node and update the uart0 node to include pinctrl and uart-has-rtscts properties. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230209131422.192941-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systemsLad Prabhakar
The GICv3 interrupts binding does not have a cpumask. The CPU mask only applies to pre-GICv3. So just drop using them from GICv3 systems. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230206002136.29401-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU nodeLad Prabhakar
Enable the performance monitor unit for the Cortex-A55 cores on the RZ/G2L (r9a07g044) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230206001300.28937-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06arm64: dts: renesas: r9a07g043u: Add Cortex-A55 PMU nodeLad Prabhakar
Enable the performance monitor unit for the Cortex-A55 core on the RZ/G2UL (r9a07g043u) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230206001133.28776-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06arm64: dts: renesas: rcar-gen3: Remove bogus "turbo-mode" propertiesGeert Uytterhoeven
On several R-Car Gen3(e) SoCs, multiple (up to 4) operating points in the same cluster are marked with the "turbo-mode" property, which is meant only for operating points beyond "Normal Mode". Fix this by dropping the property from all operating points but the "High Performance" one. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/866d06aec09e5a86dba11970f93a728b3e34e9f5.1675335086.git.geert+renesas@glider.be
2023-03-06arm64: dts: renesas: v3hsk: Add clock-skew for GEther's Micrel PHYNam Nguyen
Add the missing clock-skew property for the GEther's Micrel KSZ9031 PHY. Signed-off-by: Nam Nguyen <nam.nguyen.yh@renesas.com> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/39ab4e92d2242e1d7e83db92f91fc6e0e7e76c47.1675334998.git.geert+renesas@glider.be
2023-03-06arm64: dts: renesas: falcon: Describe CAN clockGeert Uytterhoeven
Describe the 40 MHz Crystal Clock Oscillator providing CAN_CLK. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/0bf36a1708ad87c00455b96ebaacc63fb7305b7a.1675164686.git.geert+renesas@glider.be
2023-03-06arm64: dts: renesas: rzv2mevk2: Add uSD card and eMMC supportFabrizio Castro
The RZ/V2M EVK comes with a slot for a uSD card, and an eMMC. Add support for the both of them. Please note that the pinctrl driver for RZ/V2M doesn't support interrupts yet, therefore the card detect pin has been connected to the SDHI IP directly in this patch. We'll connect the card detect pin to its corresponding GPIO when we'll have driver support for interrupts in the RZ/V2M pinctrl driver. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230130191152.182826-1-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06arm64: dts: renesas: white-hawk: Add CAN-FD supportGeert Uytterhoeven
Enable confirmed-working CAN-FD channels 0 and 1 on the White-Hawk development board: - Channel 0 uses an NXP TJR1443AT CAN transceiver, which must be enabled through a GPIO, - Channels 1-7 use Microchip MCP2558FD-H/SN CAN transceivers (not mounted for channels 4-7), which do not need explicit description, but channels 2-3 do not seem to work. Inspired by a patch in the BSP by Kazuya Mizuguch. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a19d0a70aacaf4c3517a226bf32ea49db3542da4.1674500205.git.geert+renesas@glider.be
2023-03-06arm64: dts: renesas: r8a779g0: Add CAN-FD nodeGeert Uytterhoeven
Add device nodes for the CAN-FD interface and the related external CAN clock on the Renesas R-Car V4H (R8A779G0) SoC. Based on a patch in the BSP by Kazuya Mizuguch. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/6c55d0995089917216ee261a8b8cbb980c7b5304.1674500205.git.geert+renesas@glider.be
2023-03-06arm64: dts: renesas: rzv2mevk2: Enable USB3 role switchBiju Das
Enable USB3 role switch on RZ/V2M EVK by linking USB3 peri node with hd3ss3220 controller node. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230121145853.4792-13-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06arm64: dts: renesas: rzv2mevk2: Enable USB3 DRD, Peripheral and HostBiju Das
Enable USB3 Host, Peripheral and DRD modules on RZ/V2M EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230121145853.4792-12-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit (git 2.34.1) at 2024-06-07 14:07:42 +0000