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2019-12-05Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM Device-tree updates from Olof Johansson: "As always, the bulk of updates. Some of the news this cycle: New SoC descriptions: - Broadcom BCM2711 - Amlogic Meson A1 and G12 - Freescale S32V234 - Marvell Armada AP807/AP807-quad and CP115 - Realtek RTD1293 and RTD1296 - Rockchip RK3308 New boards and platforms: - Allwinner: NanoPi Duo2 - Amlogic: Ugoos am6 - Atmel at91: Overkiz Kizbox2/4 - Broadcom: RPi4, Luxul XWC-2000 - Marvell: New Espressobin flavor - NXP: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri, S32V234 EVB, Netronix E60K02 and Kobo Clara HD, Kontron N6311 and N6411, OPOS6UL and OPOS6ULDev - Renesas: Salvator-XS - Rockchip: Beelink A1 (rk3308), rk3308 eval boards, rk3399-roc-pc" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (653 commits) ARM: dts: logicpd-torpedo: Disable USB Host arm: dts: mt6323: add keys, power-controller, rtc and codec arm64: dts: mt8183: add systimer0 device node dt-bindings: mediatek: update bindings for MT8183 systimer arm64: dts: rockchip: fix sdmmc detection on boot on rk3328-roc-cc arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board. arm64: dts: rockchip: Add Beelink A1 dt-bindings: ARM: rockchip: Add Beelink A1 arm64: dts: rockchip: Add RK3328 audio pipelines arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports arm64: dts: ti: k3-j721e-main: add USB controller nodes ARM: dts: aspeed-g6: Add timer description ARM: dts: aspeed: ast2600evb: Enable i2c buses ARM: dts: at91: add a dts and dtsi file for kizbox2 based boards dt-bindings: arm: at91: Document Kizbox2-2 board binding arm64: dts: meson-gx: fix i2c compatible arm64: dts: meson-gx: cec node should be disabled by default arm64: dts: meson-g12b-odroid-n2: add missing amlogic, s922x compatible arm64: dts: meson-gxm: fix gpu irq order arm64: dts: meson-g12a: fix gpu irq order ...
2019-11-09arm64: dts: rockchip: fix sdmmc detection on boot on rk3328-roc-ccPeter Geis
With working GPIO, during init the GPIO state s reset. This causes the sdmmc regulator to shut down, preventing detection. Removing and replacing the card will allow it to be detected, but that should not be necessary. Fix this by setting the regulator on at boot. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20191016185945.1962-1-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-11-08arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board.Markus Reichl
For rk3399-roc-pc is a mezzanine board available that carries M.2 and POE interfaces. Use it with a separate dts. Signed-off-by: Markus Reichl <m.reichl@fivetechno.de> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/0fb4e21a-fe78-00aa-6142-ca8682a913eb@fivetechno.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-11-08arm64: dts: rockchip: Add Beelink A1Robin Murphy
Beelink A1 is a TV box implementing the higher-end options of the RK3328 reference design - the DTB from the stock Android firmware is clearly the "rk3328-box-plus" variant from the Rockchip 3.10 BSP with minor modifications to accommodate the USB WiFi module and additional VFD-style LED driver. It features: - 4GB of 32-bit LPDDR3 - 16GB of HS200 eMMC (newer models with 32GB also exist) - Realtek RTL8211F phy for gigabit ethernet - Fn-Link 6221E-UUC module (RealTek RTL8821CU) for 11ac WiFi and Bluetooth 4.2 - HDMI and analog A/V - 1x USB 3.0 type A host, 1x USB 2.0 type A OTG, 1x micro SD - IR receiver and a neat little LED clock display. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/2aa21c5f3020062cf6a47057bdf3c01f0ec863ea.1571090991.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-11-08arm64: dts: rockchip: Add RK3328 audio pipelinesRobin Murphy
The audio pipelines for HDMI and the analog codec are internal to the SoC, so it makes sense to describe them at that level such that boards need only enable the respective nodes for outputs they implement. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/a09c8d795e7a66fb7bc47af2b6580f6e8dbec91e.1571090991.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-11-05arm64: dts: rockchip: Add devicetree for board roc-rk3308-ccAndy Yan
ROC-RK3308-CC is a rk3308 based board designed by Firelfy, with eMMC and 256MB DDR3 and RTL8188 Wifi on board. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20191030072811.29882-1-andy.yan@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-11-05arm64: dts: rockchip: Rework voltage supplies for regulators on rk3399-roc-pcMarkus Reichl
Correct the voltage supplies according to the board schematics ROC-3399-PC-V10-A-20180804. Signed-off-by: Markus Reichl <m.reichl@fivetechno.de> Link: https://lore.kernel.org/r/22b56700-3c9e-0f60-cd74-7ff24d4f1a23@fivetechno.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-11-05arm64: dts: rockchip: Add vcc_sys enable pin on rk3399-roc-pcMarkus Reichl
rk3399-roc-pc has vcc_sys 5V supply for USB and other peripherals. Add the GPIO pin to enable the regulator. Signed-off-by: Markus Reichl <m.reichl@fivetechno.de> Link: https://lore.kernel.org/r/c72db0ad-c261-af4f-efe6-22bbcf4a0b7b@fivetechno.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-11-05arm64: dts: rockchip: Add nodes for buttons on rk3399-roc-pcMarkus Reichl
rk3399-roc-pc has a power and a recovery button, enable them. Signed-off-by: Markus Reichl <m.reichl@fivetechno.de> Link: https://lore.kernel.org/r/1ce152cc-bd6b-63af-7892-221e084d087f@fivetechno.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-11-05arm64: dts: rockchip: enable usb2phy on px30-evbHeiko Stuebner
Enable the phy node ion the px30 evb board. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917082659.25549-13-heiko@sntech.de
2019-11-05arm64: dts: rockchip: add usb2phy for px30Heiko Stuebner
Add the usb2phy node on the px30 and hook it up to the usb controllers it supplies. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917082659.25549-12-heiko@sntech.de
2019-11-05arm64: dts: rockchip: remove px30 default optee nodeHeiko Stuebner
Having a default optee node in a soc devicetree is not really good. For one there is no guarantee that any tee got loaded and there's even the possibility that a completely different TEE got loaded. OP-Tee however will insert relevant nodes to the devicetree (firmware +reserved memory sections) during its own startup, so there really is no need to provide a default node. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20191023224409.3550-1-heiko@sntech.de
2019-11-05arm64: dts: rockchip: enable gpu on rk3399-pumaHeiko Stuebner
Set the supplying regulator and enable the gpu node on the rk3399-puma som. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20191023223954.3139-1-heiko@sntech.de
2019-11-05arm64: dts: rockchip: add px30 otp controllerHeiko Stuebner
The px30 soc contains a controller for one-time-programmable memory, so add the necessary node for it and the fields defined in it by default. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20191023224113.3268-1-heiko@sntech.de
2019-10-27arm64: dts: rockchip: Add LED nodes on rk3399-roc-pcMarkus Reichl
rk3399-roc-pc has three gpio LEDs, enable them. Signed-off-by: Markus Reichl <m.reichl@fivetechno.de> Link: https://lore.kernel.org/r/7d8d85c9-5fde-7943-a6b6-639bca38bdc1@fivetechno.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-27arm64: dts: rockchip: Add basic dts for RK3308 EVBAndy Yan
This board use uart4 as debug port and arm core voltage is modulated by pwm, logic voltage is fixed to 1.05V. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20191021084657.28629-1-andy.yan@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-27arm64: dts: rockchip: Add core dts for RK3308 SOCAndy Yan
RK3308 is a quad Cortex A35 based SOC with rich audio interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which designed for intelligent voice interaction and audio input/output processing. This patch add basic core dtsi file for it. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20191021084616.28431-1-andy.yan@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-16arm64: dts: rockchip: restyle rockchip,pins on rk3399-rock-pi-4Johan Jonker
The define RK_FUNC_1 is no longer used, so restyle the rockchip,pins definitions. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20191015205852.4200-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-10arm64: dts: rockchip: Fix override mode for rk3399-kevin panelDouglas Anderson
When I re-posted Sean's original commit to add the override mode for the kevin panel, for some reason I didn't notice that the pixel clock wasn't quite right. Looking at /sys/kernel/debug/clk/clk_summary on downstream kernels it can be seen that the VOP clock is supposed to be 266,666,667 Hz achieved by dividing the 800 MHz PLL by 3. Looking at history, it seems that even Sean's first patch [1] had this funny clock rate. I'm not sure where it came from since the commit message specifically mentioned 26666 kHz and the Chrome OS tree [2] can be seen to request 266667 kHz. In any case, let's fix it up. This together with my patch [3] to do the proper rounding when setting the clock rate makes the VOP clock more proper as seen in /sys/kernel/debug/clk/clk_summary. [1] https://lore.kernel.org/r/20180206165626.37692-4-seanpaul@chromium.org [2] https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-4.4/drivers/gpu/drm/panel/panel-simple.c#1172 [3] https://lkml.kernel.org/r/20191003114726.v2.1.Ib233b3e706cf6317858384264d5b0ed35657456e@changeid Fixes: 84ebd2da6d04 ("arm64: dts: rockchip: Specify override mode for kevin panel") Cc: Sean Paul <seanpaul@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191008124949.1.I674acd441997dd0690c86c9003743aacda1cf5dd@changeid Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-10arm64: dts: rockchip: Update nanopi4 phy reset propertiesRobin Murphy
Use the now-preferred generic phy reset properties instead of the dwmac-specific ones. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/4d16c24ae3651a2119cf5bb1213f46a9fce4b39a.1570444773.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-10arm64: dts: rockchip: Enable nanopi4 HDMI audioRobin Murphy
All the nanopi4 boards have HDMI, so let them make noise on it. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/7fe6e94e4b9f5986f19f2637b7b716f0cb54de1b.1570444701.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-10arm64: dts: rockchip: Fix usb-c on Hugsun X99 TV BoxVivek Unune
Fix usb-c on X99 TV Box. Tested with armbian w/ kernel 5.3 Signed-off-by: Vivek Unune <npcomplete13@gmail.com> Link: https://lore.kernel.org/r/20190929032230.24628-1-npcomplete13@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-10arm64: dts: rockchip: fix RockPro64 sdmmc settingsSoeren Moch
According to the RockPro64 schematic [1] the rk3399 sdmmc controller is connected to a microSD (TF card) slot. Remove the cap-mmc-highspeed property of the sdmmc controller, since no mmc card can be connected here. [1] http://files.pine64.org/doc/rockpro64/rockpro64_v21-SCH.pdf Fixes: e4f3fb490967 ("arm64: dts: rockchip: add initial dts support for Rockpro64") Signed-off-by: Soeren Moch <smoch@web.de> Link: https://lore.kernel.org/r/20191004203213.4995-1-smoch@web.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-10arm64: dts: rockchip: add cr50 tpm to rk3399-gru scarlet and bobHeiko Stuebner
Scarlet and Bob use the Google-developed cr50 chip to do things like TPM and closed-case-debugging. Add the nodes describing the cr50 and its spi-connection. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20180822120925.12388-1-heiko@sntech.de
2019-10-04arm64: dts: rockchip: fix RockPro64 sdhci settingsSoeren Moch
The RockPro64 schematics [1], [2] show that the rk3399 EMMC_STRB pin is connected to the RESET pin instead of the DATA_STROBE pin of the eMMC module. So the data strobe cannot be used for its intended purpose on this board, and so the HS400 eMMC mode is not functional. Limit the controller to HS200. [1] http://files.pine64.org/doc/rockpro64/rockpro64_v21-SCH.pdf [2] http://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf Fixes: e4f3fb490967 ("arm64: dts: rockchip: add initial dts support for Rockpro64") Signed-off-by: Soeren Moch <smoch@web.de> Link: https://lore.kernel.org/r/20191003215036.15023-2-smoch@web.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-04arm64: dts: rockchip: fix RockPro64 vdd-log regulator settingsSoeren Moch
The RockPro64 schematic [1] page 18 states a min voltage of 0.8V and a max voltage of 1.4V for the VDD_LOG pwm regulator. However, there is an additional note that the pwm parameter needs to be modified. From the schematics a voltage range of 0.8V to 1.7V can be calculated. Additional voltage measurements on the board show that this fix indeed leads to the correct voltage, while without this fix the voltage was set too high. [1] http://files.pine64.org/doc/rockpro64/rockpro64_v21-SCH.pdf Fixes: e4f3fb490967 ("arm64: dts: rockchip: add initial dts support for Rockpro64") Signed-off-by: Soeren Moch <smoch@web.de> Link: https://lore.kernel.org/r/20191003215036.15023-1-smoch@web.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-04arm64: dts: rockchip: add analog audio nodes on rk3399-rockpro64Katsuhiro Suzuki
This patch adds audio codec (Everest ES8316) and I2S audio nodes for RK3399 RockPro64. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net> Link: https://lore.kernel.org/r/20190907174833.19957-1-katsuhiro@katsuster.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-04arm64: dts: rockchip: add missing #msi-cells to rk3399Heiko Stuebner
The rk3399 gic-its was missing the #msi-cells property as found by dt-schema checks, so add it. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917083625.25818-1-heiko@sntech.de
2019-10-04arm64: dts: rockchip: fix Rockpro64 RK808 interrupt lineHugh Cole-Baker
Fix the pinctrl and interrupt specifier for RK808 to use GPIO3_B2. On the Rockpro64 schematic [1] page 16, it shows GPIO3_B2 used for the interrupt line PMIC_INT_L from the RK808, and there's a note which translates as: "PMU termination GPIO1_C5 changed to this". Tested by setting an RTC wakealarm and checking /proc/interrupts counters. Without this patch, neither the rockchip_gpio_irq counter for the RK808, nor the RTC alarm counter increment when the alarm time is reached. With this patch, both interrupt counters increment by 1 as expected. [1] http://files.pine64.org/doc/rockpro64/rockpro64_v21-SCH.pdf Fixes: e4f3fb490967 ("arm64: dts: rockchip: add initial dts support for Rockpro64") Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com> Link: https://lore.kernel.org/r/20190921131457.36258-1-sigmaris@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-03arm64: dts: rockchip: Fix roc-rk3399-pc regulator input railsJagan Teki
Few, know rk808 pmic regulators VCC[1-4], VCC[6-7], VCC[9-11], VDD_LOG, VDD_GPU, VDD_CPU_B, VCC3V3_SYS are inputting with vcc_sys which is 5V power rail from dc_12v. So, replace the vin-supply of above mentioned regulators with vcc_sys as per the PMIC-RK808-D page of roc-rk3399-pc schematics. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Link: https://lore.kernel.org/r/20190919052822.10403-7-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-03arm64: dts: rockchip: Rename vcc12v_sys into dc_12v for roc-rk3399-pcJagan Teki
It is always better practice to follow regulator naming conventions as per the schematics for future references. This would indeed helpful to review and check the naming convention directly on schematics, both for the code reviewers and the developers. So, rename vcc12v_sys into dc_12v as per rk3399 power tree as per roc-rk3399-pc schematics. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Link: https://lore.kernel.org/r/20190919052822.10403-6-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-03arm64: dts: rockchip: add px30-evb i2c1 devicesHeiko Stuebner
Enable i2c1 and adds the devices connected to it. This includes a magnetometer, goodix-touchscreen and accelerometer. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917082659.25549-10-heiko@sntech.de
2019-10-03arm64: dts: rockchip: document explicit px30 cru dependenciesHeiko Stuebner
The px30 contains 2 separate clock controllers the regular cru creating most clocks as well as the pmucru managing the GPLL and some other clocks. The gpll of course also is needed by the cru, so while we normally do rely on clock names to associate clocks getting probed later on (for example xin32k coming from an i2c device in most cases) it is safer to declare the explicit dependency between the two crus. This makes sure that for example the clock-framework probes them in the correct order from the start. The assigned-clocks properties were simply working by chance in the past so split them accordingly to the 2 crus to honor the loading direction. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20190917082659.25549-9-heiko@sntech.de
2019-10-03arm64: dts: rockchip: remove unused pin settings from px30Heiko Stuebner
These are unused gpio-settings for specific function pins, that are not used by anything and only clutter up the dtsi. They can be re-added when a relevant user is added. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917082659.25549-8-heiko@sntech.de
2019-10-03arm64: dts: rockchip: move px30-evb console output to uart 5Heiko Stuebner
The px30-evb exposes uart2 through a uart-to-usb converter on the board but these pins are shared with the sdmmc controller. With both activated this results in a race condition depending in the probe order. Whichever of the two probes first will break the other peripheral. The px30-evb also exposes uart5 through pin its pin headers, so it's way saner to use these pins for serial output and keep the sdmmc working in all cases. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917082659.25549-7-heiko@sntech.de
2019-10-03arm64: dts: rockchip: add emmc-powersequence to px30-evbHeiko Stuebner
Hook the reset line into an emmc-pwrseq for it to get initialized nicely. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917082659.25549-6-heiko@sntech.de
2019-10-03arm64: dts: rockchip: fix the px30-evb power treeHeiko Stuebner
Add the board's pmic (rk809) and hook up the real supplies to their consumers. This is especially important as cpufreq would otherwise hang the system when scaling the frequency without adjusting the voltage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917082659.25549-5-heiko@sntech.de
2019-10-03arm64: dts: rockchip: add default px30 emmc pinctrlHeiko Stuebner
emmc chips are normally hooked up in standard ways using the full 8bit bus connection, so there should be no need for all future boards to define this on their own. So add default pin setups for 8bit busses and special boards really only needing 4 or 1 bit connections can override. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917082659.25549-4-heiko@sntech.de
2019-10-03arm64: dts: rockchip: remove px30 emmc_pwren pinctrlHeiko Stuebner
That gpio1-b0 can only be flash_cs apart from a regular gpio, so there is no power-related pinmux for the emmc for this pin. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917082659.25549-3-heiko@sntech.de
2019-10-03arm64: dts: rockchip: remove static xin32k from px30Heiko Stuebner
Similar to all other Rockchip SoCs the px30 does not have a static 32kHz clock. Instead it again gets supplied from an external component like the pmic. So drop the static clock, so that we can hook up the right one. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917082659.25549-2-heiko@sntech.de
2019-10-03arm64: dts: rockchip: fix iface clock-name on px30 iommusHeiko Stuebner
The iommu clock names are aclk+iface not aclk+hclk as in the vendor kernel, so fix that in the px30.dtsi Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917082659.25549-1-heiko@sntech.de
2019-09-01arm64: dts: rockchip: limit clock rate of MMC controllers for RK3328Shawn Lin
150MHz is a fundamental limitation of RK3328 Soc, w/o this limitation, eMMC, for instance, will run into 200MHz clock rate in HS200 mode, which makes the RK3328 boards not always boot properly. By adding it in rk3328.dtsi would also obviate the worry of missing it when adding new boards. Fixes: 52e02d377a72 ("arm64: dts: rockchip: add core dtsi file for RK3328 SoCs") Cc: stable@vger.kernel.org Cc: Robin Murphy <robin.murphy@arm.com> Cc: Liang Chen <cl@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-08-22arm64: dts: rockchip: add rk3328 VPU nodeJonas Karlman
This patch add a VPU device node for rk3328. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-08-19arm64: dts: rockchip: fix vcc_host_5v regulator for usb3 hostKever Yang
According to rock64 schemetic V2 and V3, the VCC_HOST_5V output is controlled by USB_20_HOST_DRV, which is the same as VCC_HOST1_5V. V1 hardware was never sold and only V2/V3 is with customers, so there is no need to keep a seaprate v1 version around. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-08-16arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBCAndy Yan
P710 is a RK3399 based SBC, designed by Leez [0]. Specification - Rockchip RK3399 - 4/2GB LPDDR4 - TF sd scard slot - eMMC - M.2 B-Key for 4G LTE - AP6256 for WiFi + BT - Gigabit ethernet - HDMI out - 40 pin header - USB 2.0 x 2 - USB 3.0 x 1 - USB 3.0 Type-C x 1 - TYPE-C Power supply [0]https://leez.lenovo.com Signed-off-by: Andy Yan <andyshrk@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-08-16arm64: dts: rockchip: enable internal SPI flash for RockPro64.Andrius Štikonas
The rockpro64 contains a nor-flash chip connected to spi1. Signed-off-by: Andrius Štikonas <andrius@stikonas.eu> [a number of cleanups] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-07-25arm64: dts: rockchip: Add PWM fan for RockPro64Andrius Štikonas
RockPro64 has a dedicated circuit for driving a 12V fan from PWM1. At the moment this makes fan spin at full speed. fancontrol can be used to control fan speed. E.g. the following config file works well: INTERVAL=10 DEVPATH=hwmon0=devices/platform/pwm-fan DEVNAME=hwmon0=pwmfan FCTEMPS=hwmon0/device/pwm1=../thermal/thermal_zone0/temp MINTEMP=hwmon0/device/pwm1=40 MAXTEMP=hwmon0/device/pwm1=60 MINSTART=hwmon0/device/pwm1=100 MINSTOP=hwmon0/device/pwm1=70 In the future it would be nice to define trip points in dts file, so that kernel could adjust fan speed itself. Signed-off-by: Andrius Štikonas <andrius@stikonas.eu> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-07-22arm64: dts: rockchip: Specify override mode for kevin panelSean Paul
This patch adds an override mode for kevin devices. The mode increases both back porches to allow a pixel clock of 26666kHz as opposed to the 'typical' value of 252750kHz. This is needed to avoid interference with the touch digitizer on these laptops. Cc: Doug Anderson <dianders@chromium.org> Cc: Eric Anholt <eric@anholt.net> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Jeffy Chen <jeffy.chen@rock-chips.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Stéphane Marchesin <marcheu@chromium.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Sean Paul <seanpaul@chromium.org> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-27arm64: dts: rockchip: Fix USB3 Type-C on rk3399-sapphireVicente Bergas
Before this patch, the Type-C port on the Sapphire board is dead. If setting the 'regulator-always-on' property to 'vcc5v0_typec0' then the port works for about 4 seconds at start-up. This is a sample trace with a memory stick plugged in: 1.- The memory stick LED lights on and kernel reports: [ 4.782999] scsi 0:0:0:0: Direct-Access USB DISK PMAP PQ: 0 ANSI: 4 [ 5.904580] sd 0:0:0:0: [sdb] 3913344 512-byte logical blocks: (2.00 GB/1.87 GiB) [ 5.906860] sd 0:0:0:0: [sdb] Write Protect is off [ 5.908973] sd 0:0:0:0: [sdb] Mode Sense: 23 00 00 00 [ 5.909122] sd 0:0:0:0: [sdb] No Caching mode page found [ 5.911214] sd 0:0:0:0: [sdb] Assuming drive cache: write through [ 5.951585] sdb: sdb1 [ 5.954816] sd 0:0:0:0: [sdb] Attached SCSI removable disk 2.- 4 seconds later the memory stick LED lights off and kernel reports: [ 9.082822] phy phy-ff770000.syscon:usb2-phy@e450.2: charger = USB_DCP_CHARGER 3.- After a minute the kernel reports: [ 71.666761] usb 5-1: USB disconnect, device number 2 It has been checked that, although the LED is off, VBUS is present. If, instead, the dr_mode is changed to host and the phy-supply changed accordingly, then it works. It has only been tested in host mode. Signed-off-by: Vicente Bergas <vicencb@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-27arm64: dts: rockchip: Update DWC3 modules on RK3399 SoCsEnric Balletbo i Serra
As per binding documentation [1], the DWC3 core should have the "ref", "bus_early" and "suspend" clocks. As explained in the binding, those clocks are required for new platforms but not for existing platforms before commit fe8abf332b8f ("usb: dwc3: support clocks and resets for DWC3 core"). However, as those clocks are really treated as required, this ends with having some annoying messages when the "rockchip,rk3399-dwc3" is used: [ 1.724107] dwc3 fe800000.dwc3: Failed to get clk 'ref': -2 [ 1.731893] dwc3 fe900000.dwc3: Failed to get clk 'ref': -2 [ 2.495937] dwc3 fe800000.dwc3: Failed to get clk 'ref': -2 [ 2.647239] dwc3 fe900000.dwc3: Failed to get clk 'ref': -2 In order to remove those annoying messages, update the DWC3 hardware module node and add all the required clocks. With this change, both, the glue node and the DWC3 core node, have the clocks defined, but that's not really a problem and there isn't a side effect on do this. So, we can get rid of the annoying get clk error messages. [1] Documentation/devicetree/bindings/usb/dwc3.txt Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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