summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/rockchip
AgeCommit message (Collapse)Author
2024-02-04arm64: dts: rockchip: Add Touch to Anbernic RG-ARC DChris Morgan
Add the Goodix GT927 touchscreen to the Anbernic RG-ARC D. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Tested-by: Trooper_Max <troopermax@gmail.com> Link: https://lore.kernel.org/r/20240201150620.886786-1-macroalpha82@gmail.com [renamed node to generic touchscreen@14] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: fix nanopc-t6 sdmmc regulatorJohn Clark
sdmmc on the nanopc-t6 is powered by vcc3v3_sd_s0, not vcc_3v3_s3 add the vcc3v3_sd_s0 regulator, and control it with gpio4_a5 Signed-off-by: John Clark <inindev@gmail.com> Link: https://lore.kernel.org/r/20240102024054.1030313-1-inindev@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: remove duplicate SPI aliases for helios64Quentin Schulz
An earlier commit defined an alias for all SPI controllers found on the RK3399, so there's no need to duplicate the aliases in helios64's device tree. Cc: Quentin Schulz <foss+kernel@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Link: https://lore.kernel.org/r/20240109-rk3399-spi-aliases-v1-2-2009e44e734a@theobroma-systems.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: add spi controller aliases on rk3399Quentin Schulz
There are 6 SPI controllers on RK3399 and they are all numbered in the TRM, so let's add the appropriate aliases to the main DTSI so that any RK3399-based board doesn't need to define the aliases themselves to benefit from stable SPI indices in userspace. Cc: Quentin Schulz <foss+kernel@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Link: https://lore.kernel.org/r/20240109-rk3399-spi-aliases-v1-1-2009e44e734a@theobroma-systems.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: Add support for NanoPi R6CMuhammed Efe Cetin
NanoPi R6C is mostly same as R6S variant. It has M2 port instead of a NIC port and different led labeling. Signed-off-by: Muhammed Efe Cetin <efectn@protonmail.com> Link: https://lore.kernel.org/r/0f9ee0baa6c9de4d54dd6d13957ca15a63ec934f.1703934548.git.efectn@protonmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: Add support for NanoPi R6SMuhammed Efe Cetin
Add basic NanoPi R6S support that comes with USB2, PCIe, SD card, eMMC support. Signed-off-by: Muhammed Efe Cetin <efectn@protonmail.com> Link: https://lore.kernel.org/r/6db3b653efc6f0a2dca8e96fdd0503906db72fb6.1703934548.git.efectn@protonmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: Increase maximum frequency of SPI flash for ROCK Pi 4A/B/CStefan Nagy
The ROCK Pi 4A/B/C boards come with a 32 Mbit SPI NOR flash chip (XTX Technology Limited XT25F32) with a maximum clock frequency of 108 MHz. Use this value for the device node's spi-max-frequency property. This patch has been tested on ROCK Pi 4A. Signed-off-by: Stefan Nagy <stefan.nagy@ixypsilon.net> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/20231217113208.64056-1-stefan.nagy@ixypsilon.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: add sdmmc card detect to the nanopc-t6John Clark
The nanopc-t6 has an sdmmc card detect connected to gpio0_a4 which is active low. Signed-off-by: John Clark <inindev@gmail.com> Link: https://lore.kernel.org/r/20231230165053.3781-1-inindev@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: Add cache information to the SoC dtsi for RK3399Dragan Simic
Add missing cache information to the Rockchip RK3399 SoC dtsi. The specified values were derived by hand from the cache size specifications available from the RK3399 datasheet; for future reference, here's a brief summary: - Each Cortex-A72 core has 48 KB of L1 instruction cache and 32 KB of L1 data cache available, four-way set associative - Each Cortex-A53 core core has 32 KB of instruction cache and 32 KB of L1 data cache available, four-way set associative - The big (A72) cluster has 1 MB of unified L2 cache available - The little (A53) cluster has 512 KB of unified L2 cache available This patch allows /proc/cpuinfo and lscpu(1) to display proper RK3399 cache information, and it eliminates the following error in the kernel log: cacheinfo: Unable to detect cache hierarchy for CPU 0 While there, add a couple of somewhat useful comments, which may help a bit anyone going through the RK3399 SoC dtsi. Co-developed-by: Kyle Copperfield <kmcopper@danwin1210.me> Signed-off-by: Kyle Copperfield <kmcopper@danwin1210.me> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/be3cbcae5c40fa72a52845d30dcc66c847a98cfa.1702616304.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5bAlexey Charkov
By default the GPIO pin that connects to the WiFi enable signal inside the M.2 Key E slot is driven low, resulting in impossibility to connect to any network. Add a DT node to expose it as an RFKILL device, which lets the WiFi driver or userspace toggle it as required. Signed-off-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20240106202650.22310-1-alchark@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: enable NanoPC-T6 MiniPCIe powerHugh Cole-Baker
The NanoPC-T6 has a Mini PCIe slot intended to be used for a 4G or LTE modem. This slot has no PCIe functionality, only USB 2.0 pins are wired to the SoC, and USIM pins are wired to a SIM card slot on the board. Define the 3.3v supply for the slot so it can be used. Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com> Link: https://lore.kernel.org/r/20240109202729.54292-1-sigmaris@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: mark system power controller on rk3588-evb1Sebastian Reichel
Mark the primary PMIC as system-power-controller, so that the system properly shuts down on poweroff. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240117191555.86138-1-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: Add LED_GREEN for edgeble-neu6aJagan Teki
Edgeble NCM6A, NCM6B SoM has Green LED on the module. Enable them with heartbeat function. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20231125190522.87607-11-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: Add Edgeble NCM6A-IO USB2Jagan Teki
Edgeble NCM6A-IO board has 2 port USB2.0 Host and USB2.0 on E-Key. Add support for it. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20231125190522.87607-10-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 B-Key, E-KeyJagan Teki
Edgeble NCM6A-IO board has M.2 B-Key, E-Key via PCI3x2. Add support for it. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20231125190522.87607-9-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 M-KeyJagan Teki
Edgeble NCM6A-IO board has M.2 M-Key via PCI3x4. Add support for it. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20231125190522.87607-8-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: Add Edgeble NCM6A-IO 2.5G ETHJagan Teki
Edgeble NCM6A-IO board has 2.5Gbps Ethernet via PCI2_0. Add support for it. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20231125190522.87607-7-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: Add vdd_cpu_big reg to rk3588-edgeble-ncm6Jagan Teki
The RK8602 and RK8603 voltage regulators on the Rock 5B board provide the power lines vdd_cpu_big0 and vdd_cpu_big1, respectively. Add the necessary device tree nodes and bind them to the corresponding CPU big core nodes. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20231125190522.87607-6-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: Add Edgeble NCM6A WiFi6 OverlayJagan Teki
Edgeble NCM6A SOM has on-module M.2 1216-compatible WiFi modules. Currently, AW-XM548NF WiFi6 and Intel 8260D2W WiFi5 modules are supported. WiFi modules are fixed on SoM, not pluggable M.2 slots, so different SoM's for each type of WiFi module. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20231125190522.87607-5-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: Add common DT for edgeble-neu6b-ioJagan Teki
Edgeble Neu6a and Neu6b are compatible with common IO board. So, maintain the IO board in rk3588-edgeble-neu6a-io.dtsi. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20231125190522.87607-4-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: Add edgeble-neu6a-common DTJagan Teki
Edgeble NCM6A-IO is common compatible IO board for both NCM6A and NCM6B. Add a common io DTSI for it to include them in both NCM6A and NCM6B DTS files. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20231125190522.87607-3-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: Drop edgeble-neu6b dcdc-reg4 regulator-init-microvoltJagan Teki
The 'regulator-init-microvolt' property is not currently supported by any driver, it was simply carried on from downstream kernels. rk3588-edgeble-neu6b-io.dtb: pmic@0: regulators:dcdc-reg4: Unevaluated properties are not allowed ('regulator-init-microvolt' was unexpected) Remove the invalid property. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20231125190522.87607-2-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: add missing definition of pmu io domains 1 and 2 on ↵Iskander Amara
ringneck Two pmuio domains on ringneck are not defined: 1- PMUIO1: supplied by vcc_3v3 regulator(PMIC RK809) 2- PMUIO2: supplied by vcc_3v3 regulator(PMIC RK809) The reason why no functional effect was observed is because of that the above mentionned PMUIO domains were supplied by a regulator which is always on. So let's add their definition in the dtsi. Signed-off-by: Iskander Amara <iskander.amara@theobroma-systems.com> Link: https://lore.kernel.org/r/20240103164734.1151290-1-iskander.amara@theobroma-systems.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: add Anbernic RG-ARC S and RG-ARC DChris Morgan
Add support for the Anbernic RG-ARC S and RG-ARC D devices. These devices feature the following: - Rockchip RK3566 SoC - 4 inch 480x640 display (rotated) - Goodix multi-touch (ARC D only, untested as I lack the device) - 1GB (ARC S) or 2GB (ARC D) of RAM - 2 SDMMC slots - eMMC (ARC D only) - Realtek 8821CS WiFi/Bluetooth - External stereo speakers - 6 face buttons (A, B, C, X, Y, Z) along with a D-Pad and start and select buttons. - A PWM vibrator. Note that the Goodix touchscreen on I2C2 is not defined, as I lack the necessary hardware to confirm it works correctly with the mainline driver. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20240123212111.202146-5-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: rockchip: Move device specific propertiesChris Morgan
Move device specific properties related to the ADC Joystick to different board specific device trees. This is in preparation for adding the Anbernic RG-Arc series of devices. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20240123212111.202146-2-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25arm64: dts: Fix TPM schema violationsLukas Wunner
Since commit 26c9d152ebf3 ("dt-bindings: tpm: Consolidate TCG TIS bindings"), several issues are reported by "make dtbs_check" for arm64 devicetrees: The compatible property needs to contain the chip's name in addition to the generic "tcg,tpm_tis-spi" and the nodename needs to be "tpm@0" rather than "cr50@0": tpm@1: compatible: ['tcg,tpm_tis-spi'] is too short from schema $id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml# cr50@0: $nodename:0: 'cr50@0' does not match '^tpm(@[0-9a-f]+)?$' from schema $id: http://devicetree.org/schemas/tpm/google,cr50.yaml# Fix these schema violations. phyGATE-Tauri uses an Infineon SLB9670: https://lore.kernel.org/all/ab45c82485fa272f74adf560cbb58ee60cc42689.camel@phytec.de/ Gateworks Venice uses an Atmel ATTPM20P: https://trac.gateworks.com/wiki/tpm Signed-off-by: Lukas Wunner <lukas@wunner.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-01-11Merge tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC DT updates from Arnd Bergmann: "There is one new SoC for each 32-bit Arm and 64-bit RISC-V, but both the Rockchips rv1109 and Sopgho CV1812H are just minor variations of already supported chips. The other six new SoCs are all part of existing arm64 families, but are somewhat more interesting: - Samsung ExynosAutov920 is an automotive chip, and the first one we support based on the Cortex-A78AE core with lockstep mode. - Google gs101 (Tensor G1) is the chip used in a number of Pixel phones, and is grouped with Samsung Exynos here since it is based on the same SoC design, sharing most of its IP blocks with that series. - MediaTek MT8188 is a new chip used for mid-range tablets and Chromebooks, using two Cortex-A78 cores where the older MT8195 had four of them. - Qualcomm SM8650 (Snapdragon 8 Gen 3) is their current top range phone SoC and the first supported chip based on Cortex-X4, Cortex-A720 and Cortex-A520. - Qualcomm X1E80100 (Snapdragon X Elite) in turn is the latest Laptop chip using the custom Oryon cores. - Unisoc UMS9620 (Tanggula 7 series) is a 5G phone SoC based on Cortex-A76 and Cortex-A55 In terms of boards, we have - Five old Microsoft Lumia phones, the HTC One Mini 2, Motorola Moto G 4G, and Huawei Honor 5X/GR5, all based on Snapdragon SoCs. - Multiple Rockchips mobile gaming systems (Anbernic RG351V, Powkiddy RK2023, Powkiddy X55) along with the Sonoff iHost Smart Home Hub and a few Rockchips SBCs - Some ComXpress boards based on Marvell CN913x, which is the follow-up to Armada 7xxx/8xxx. - Six new industrial/embedded boards based on NXP i.MX8 and i.MX9 - Mediatek MT8183 based Chromebooks from Lenovo, Asus and Acer. - Toradex Verdin AM62 Mallow carrier for TI AM62 - Huashan Pi board based on the SophGo CV1812H RISC-V chip - Two boards based on Allwinner H616/H618 - A number of reference boards for various added SoCs from Qualcomm, Mediatek, Google, Samsung, NXP and Spreadtrum As usual, there are cleanups and warning fixes across all platforms as well as added features for several of them" * tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (857 commits) ARM: dts: usr8200: Fix phy registers arm64: dts: intel: minor whitespace cleanup around '=' arm64: dts: socfpga: agilex: drop redundant status arm64: dts: socfpga: agilex: add unit address to soc node arm64: dts: socfpga: agilex: move firmware out of soc node arm64: dts: socfpga: agilex: move FPGA region out of soc node arm64: dts: socfpga: agilex: align pin-controller name with bindings arm64: dts: socfpga: stratix10_swvp: drop unsupported DW MSHC properties arm64: dts: socfpga: stratix10_socdk: align NAND chip name with bindings arm64: dts: socfpga: stratix10: add unit address to soc node arm64: dts: socfpga: stratix10: move firmware out of soc node arm64: dts: socfpga: stratix10: move FPGA region out of soc node arm64: dts: socfpga: stratix10: align pincfg nodes with bindings arm64: dts: socfpga: stratix10: add clock-names to DWC2 USB arm64: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size ARM: dts: socfpga: align NAND controller name with bindings ARM: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size arm64: dts: rockchip: Fix led pinctrl of lubancat 1 arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6 arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b ...
2023-12-29arm64: dts: rockchip: Fix led pinctrl of lubancat 1Andy Yan
According to the schematics, the gpio control sys_led is GPIO0_C5. Fixes: 8d94da58de53 ("arm64: dts: rockchip: Add EmbedFire LubanCat 1") Reported-by: Zhang Ning <zhangn1985@outlook.com> Closes: https://lore.kernel.org/linux-rockchip/OS0P286MB06412D049D8BF7B063D41350CD95A@OS0P286MB0641.JPNP286.PROD.OUTLOOK.COM/T/#u Signed-off-by: Andy Yan <andyshrk@163.com> Link: https://lore.kernel.org/r/20231225005055.3102743-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-29arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6John Clark
Both rk806_dvs1_null and rk806_dvs2_null duplicate gpio_pwrctrl2 and gpio_pwrctrl1 is not set. This patch sets gpio_pwrctrl1. Signed-off-by: John Clark <inindev@gmail.com> Link: https://lore.kernel.org/r/20231225223226.17690-1-inindev@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-29arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5bJohn Clark
Both rk806_dvs1_null and rk806_dvs2_null duplicate gpio_pwrctrl2 and gpio_pwrctrl1 is not set. This patch sets gpio_pwrctrl1. Signed-off-by: John Clark <inindev@gmail.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20231225222859.17153-2-inindev@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-29arm64: dts: rockchip: support poweroff on the rock-5bJohn Clark
Allow the rock-5b to poweroff its pmic. When issuing a "shutdown -h now" on the rock-5b it reboots instead. Defining 'system-power-controller' allows the rk806 to power down. Commit c699fbfdfd54 ("arm64: dts: rockchip: Support poweroff on NanoPC-T6") similarly resolves this issue for the nanopc-t6. Signed-off-by: John Clark <inindev@gmail.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20231225222859.17153-1-inindev@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-29arm64: dts: rockchip: Support poweroff on Orange Pi 5Jimmy Hon
The RK806 on the Orange Pi 5 can be used to power on/off the whole board. Mark it as the system power controller. Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Link: https://lore.kernel.org/r/20231227203211.1047-1-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-29arm64: dts: rockchip: nanopc-t6 sdmmc beautificationJohn Clark
drop max-frequency = <200000000> as it is already defined in rk3588s.dtsi order no-sdio & no-mmc properties while we are here Signed-off-by: John Clark <inindev@gmail.com> Link: https://lore.kernel.org/r/20231228173011.2863-1-inindev@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-24arm64: dts: rockchip: Fix rk3588 USB power-domain clocksSam Edwards
The QoS blocks saved/restored when toggling the PD_USB power domain are clocked by ACLK_USB. Attempting to access these memory regions without that clock running will result in an indefinite CPU stall. The PD_USB node wasn't specifying this clock dependency, resulting in hangs when trying to toggle the power domain (either on or off), unless we get "lucky" and have ACLK_USB running for another reason at the time. This "luck" can result from the bootloader leaving USB powered/clocked, and if no built-in driver wants USB, Linux will disable the unused PD+CLK on boot when {pd,clk}_ignore_unused aren't given. This can also be unlucky because the two cleanup tasks run in parallel and race: if the CLK is disabled first, the PD deactivation stalls the boot. In any case, the PD cannot then be reenabled (if e.g. the driver loads later) once the clock has been stopped. Fix this by specifying a dependency on ACLK_USB, instead of only ACLK_USB_ROOT. The child-parent relationship means the former implies the latter anyway. Fixes: c9211fa2602b8 ("arm64: dts: rockchip: Add base DT for rk3588 SoC") Cc: stable@vger.kernel.org Signed-off-by: Sam Edwards <CFSworks@gmail.com> Link: https://lore.kernel.org/r/20231216021019.1543811-1-CFSworks@gmail.com [changed to only include the missing clock, not dropping the root-clocks] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-24arm64: dts: rockchip: configure eth pad driver strength for orangepi r1 plus ltsTianling Shen
The default strength is not enough to provide stable connection under 3.3v LDO voltage. Fixes: 387b3bbac5ea ("arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS") Cc: stable@vger.kernel.org # 6.6+ Signed-off-by: Tianling Shen <cnsztl@gmail.com> Link: https://lore.kernel.org/r/20231216040723.17864-1-cnsztl@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-24arm64: dts: rockchip: Support poweroff on NanoPC-T6Hugh Cole-Baker
The RK806 on the NanoPC-T6 can be used to power on/off the whole board. Mark it as the system power controller. Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com> Link: https://lore.kernel.org/r/20231216212134.23314-1-sigmaris@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-24arm64: dts: rockchip: rk3308-rock-pi-s gpio-line-names cleanupTrevor Woerner
Perform the following cleanups on a previous patch: - indent lines after "gpio-line-names" - fix D0-D8 -> D0-D7 - sort phandle references Fixes: c45de75d7a9a ("arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s") Signed-off-by: Trevor Woerner <twoerner@gmail.com> Link: https://lore.kernel.org/r/20231219173814.1569-1-twoerner@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-24arm64: dts: rockchip: Add support for rk3588 based board Cool Pi CM5 EVBAndy Yan
Cool Pi CM5 EVB works as a mother board connect with CM5. CM5 Specification: - Rockchip RK3588 - LPDDR4 2/4/8/16 GB - TF scard slot - eMMC 8/32/64/128 GB module - Gigabit ethernet x 1 with PHY YT8531 - Gigabit ethernet x 1 drived by PCIE with YT6801S CM5 EVB Specification: - HDMI Type A out x 2 - HDMI Type D in x 1 - USB 2.0 Host x 2 - USB 3.0 OTG x 1 - USB 3.0 Host x 1 - PCIE M.2 E Key for Wireless connection - PCIE M.2 M Key for NVME connection - 40 pin header Signed-off-by: Andy Yan <andyshrk@163.com> Link: https://lore.kernel.org/r/20231212124407.1897604-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-24arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4BAndy Yan
CoolPi 4B is a rk3588s based SBC. Specification: - Rockchip RK3588S - LPDDR4 2/4/8/16 GB - TF scard slot - eMMC 8/32/64/128 GB module - Gigabit ethernet drived by PCIE with RTL8111HS - HDMI Type D out - Mini DP out - USB 2.0 Host x 2 - USB 3.0 OTG x 1 - USB 3.0 Host x 1 - WIFI/BT module AIC8800 - 40 pin header Signed-off-by: Andy Yan <andyshrk@163.com> arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4B Link: https://lore.kernel.org/r/20231212124253.1897438-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-24arm64: dts: rockchip: add gpio-line-names to rk3328-rock-pi-eTrevor Woerner
Add names to the pins of the general-purpose expansion header as given in the Radxa GPIO page[1] following the conventions in the kernel documentation[2] to make it easier for users to correlate the pins with functions when using utilities such as 'gpioinfo'. Signed-off-by: Trevor Woerner <twoerner@gmail.com> Link: https://lore.kernel.org/r/20231213160556.14424-1-twoerner@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-15arm64: dts: rockchip: make use gpio-keys for buttons on puma-haikouVahe Grigoryan
Haikou is an evaluation and development platform for System on Modules (SOMs). Haikou devkit exposes multiple buttons so let's register them as such so that the input subsystem can generate events when pressed or switched. Signed-off-by: Vahe Grigoryan <vahe.grigoryan@theobroma-systems.com> Link: https://lore.kernel.org/r/20231214122801.3144180-3-vahe.grigoryan@theobroma-systems.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-15arm64: dts: rockchip: expose BIOS Disable feedback pin on rk3399-pumaVahe Grigoryan
The Puma SoM allows to select in hardware directly which storage medium to try for loading the bootloader, either SPI-NOR followed by eMMC followed by SD card, or SD card only. This signal is exposed on the Q7 connector and allows carrierboards to control it however they want. This feedback pin allows to know in which state the SoM currently is and provided the current state isn't modified until next reboot, know from which storage medium the bootloader could be loaded from next time. Signed-off-by: Vahe Grigoryan <vahe.grigoryan@theobroma-systems.com> Link: https://lore.kernel.org/r/20231214122801.3144180-2-vahe.grigoryan@theobroma-systems.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-15arm64: dts: rockchip: fix misleading comment in rk3399-puma-haikou.dtsVahe Grigoryan
Haikou is an evaluation and development platform for System on Modules (SOMs). The GPIO0_B1 is routed to the Wake button instead of BIOS_DISABLE, update the comment to reflect that. Signed-off-by: Vahe Grigoryan <vahe.grigoryan@theobroma-systems.com> Link: https://lore.kernel.org/r/20231214122801.3144180-1-vahe.grigoryan@theobroma-systems.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-15arm64: dts: rockchip: Add vop on rk3588Andy Yan
Add vop dt node for rk3588. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20231211120004.1785616-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-12arm64: dts: rockchip: Add Anbernic RG351VChris Morgan
Add support for the Anbernic RG351V, which is a handheld gaming console from Anbernic with an RK3326 SoC, a 640x480 LCD display, a single analog joystick with several face buttons, two USB C ports, and internal WiFi over USB. All hardware has been tested as working except for the battery, which will require further modification to the mainline rk817 battery driver before it can be used (the device was built without a shunt resistor, and as such the battery cannot measure current; only voltage). Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20231120230131.57705-4-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-12arm64: dts: rockchip: Split RG351M from Odroid Go AdvanceChris Morgan
Split the RG351M into its own DTSI file. The RG351M, unlike the Odroid Go Advance, has no ADC joysticks, no GPIO buttons (except for volume on the RG351V), a PWM vibrator that interferes with an Odroid regulator, and different LEDs. Split the RG351M into a DTSI file that can then be imported into the DTS files for the RG351M and a new RG351V. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20231120230131.57705-3-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-12arm64: dts: rockchip: Add ethernet0 alias to the dts for RK3588(S) boardsDragan Simic
Add ethernet0 alias to the board dts files for a few supported RK3588 and RK3588S boards that had it missing. Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/9af2026bf8a5538aff627381289cb06f2fab4263.1702368023.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-12arm64: dts: rockchip: Add ethernet0 alias to the dts for RK3566 boardsDragan Simic
Add ethernet0 alias to the board dts files for a few supported RK3566 boards that had it missing. Also, remove the ethernet0 alias from one RK3566 SoM dtsi file, which doesn't enable the GMAC, and add the ethernet0 alias back to the dependent board dts files, which actually enable the GMAC. Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/d2a272e0ae0fff0adfab8bb0238243b11d348799.1702368023.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-12arm64: dts: rockchip: Remove ethernet0 alias from the SoC dtsi for PX30Dragan Simic
Not all supported boards actually use the PX30's built-in (G)MAC, while the SoC TRM and the datasheet don't define some standard numbering in this case. Thus, remove the ethernet0 alias from the PX30 SoC dtsi file, and add the same alias back to the appropriate board dts(i) files. This is quite similar to the already performed migration of the mmcX aliases from the Rockchip SoC dtsi files to the board dts(i) files. Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/0d9da8959b4f567622676c34b5feb74c49489554.1702366958.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-12arm64: dts: rockchip: Remove ethernetX aliases from the SoC dtsi for RK3328Dragan Simic
Not all supported boards actually use the RK3328's built-in GMACs, while the SoC TRM and the datasheet don't define some standard numbering in this case. Thus, remove the ethernet0 and ethernet1 aliases from the RK3328 SoC dtsi file, and add the same alias back to the appropriate board dts(i) files. These changes also touch one RK3318-based board dts, because it actually depends on the RK3328 SoC dtsi and enables one of the GMACs. This is quite similar to the already performed migration of the mmcX aliases from the Rockchip SoC dtsi files to the board dts(i) files. Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/0c14f2e354d32f5d45c718ce16643553ca72f6a5.1702366958.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit (git 2.34.1) at 2024-06-23 09:21:46 +0000