linux-arm.git - Russell King's ARM Linux kernel tree

Age	Commit message (Collapse)	Author
2023-06-15	arm64: dts: ti: k3-am62a-main: Add sa3_secproxy	Nishanth Menon
	Security Management Subsystem(SMS) has it's own unique secure proxy as part of Security Accelerator (SA3) module. This is used for communicating with ROM and for special usecases such as HSM operations. This is in addition to the one in the main domain DMSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230530165900.47502-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08	arm64: dts: ti: k3-am62a: Add watchdog nodes	Nishanth Menon
	Add nodes for watchdogs: - 5 in main domain - 1 in MCU domain - 1 in wakeup domain Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230418012717.1230882-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08	arm64: dts: ti: k3-am62a: Add general purpose timers	Nishanth Menon
	Similar to commit 3308a31c507c ("arm64: dts: ti: k3-am62: Add general purpose timers for am62"), there are 12 general purpose timers on am62a7 split between 8 in main and 4 in mcu domains. The 4 in mcu domain do not have interrupts that are routable to a53. We configure the timers with the 25 MHz input clock by default as the 32.768 kHz clock may not be wired on the device. We leave the MCU domain timers clock mux unconfigured, and mark the MCU domain timers reserved. The MCU domain timers are likely reserved by the software for the ESM module. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230418012717.1230882-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-01-16	arm64: dts: ti: k3-am62a-main: Add more peripheral nodes	Vignesh Raghavendra
	Add DT nodes for main domain SPI, PWM, DMA, CPSW (ethernet), mailbox, spinlock, USB and CAN. Co-developed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230103042110.1092122-3-vigneshr@ti.com
2022-09-13	arm64: dts: ti: Introduce AM62A7 family of SoCs	Vignesh Raghavendra
	The AM62A SoC belongs to the K3 Multicore SoC architecture platform that can run edge AI applications with Video/Vision processing. This provides advanced system integration with high security support to enable a broad set of applications in industrial/automotive markets such as, driver monitoring, machine vision, smart camera, eMirror, front camera, robotics, and building automation. Some highlights of AM62A SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single core variants are provided in the same package to allow HW compatible designs. * One Device manager Cortex-R5F for system power and resource management, and one Cortex-R5F for Functional Safety or general-purpose usage. * One AI accelerator (up to 2 TOPS), using one C7x256V DSP w/Matrix Multiplier accelerator (MMA) for Deep Learning usage. * VPAC3L(Vision Pre-processing Accelerator), providing 12-bit ISP up to 315MPixel/s RGB+IR support, and Noise Filter for improved integrated imaging and vision image processing. * H.264/H.265 Video Encode/Decode. + Motion JPEG encode * Display support, providing 24-bit RBG parallel interface up to 200MHz pixel clock support for 2K display resolution. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3x McASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized Hardware Security Module with support for secure boot, debug security and crypto acceleration and trusted execution environment * One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types. * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling battery powered system design. More details about the SoCs can be found in the Technical Reference Manual: https://www.ti.com/lit/zip/spruj16 Co-developed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Devarsh Thakkar <devarsht@ti.com> Link: https://lore.kernel.org/r/20220901141328.899100-5-vigneshr@ti.com