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2020-10-26arm64: dts: ti: k3-am65: ringacc: drop ti, dma-ring-reset-quirkGrygorii Strashko
Remove obsolete "ti,dma-ring-reset-quirk" Ringacc DT property. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200829184139.15547-4-grygorii.strashko@ti.com
2020-09-07arm64: dts: ti: k3-*: Fix up node_name_chars_strict warningsNishanth Menon
Building with W=2 throws up a bunch of easy to fixup warnings.. node_name_chars_strict is one of them.. Knock those out. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200903130015.21361-9-nm@ti.com
2020-09-07arm64: dts: ti: k3-*: Use generic pinctrl for node namesNishanth Menon
Use pinctrl@ naming for nodes following standard conventions of device tree (section 2.2.2 Generic Names recommendation in [1]). [1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3 Suggested-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200903130015.21361-6-nm@ti.com
2020-09-07arm64: dts: ti: k3-am65*: Use generic clock for syscon clock namesNishanth Menon
serdes and ehrpwm_tbclk nodes should be using clock@ naming for nodes following standard conventions of device tree (section 2.2.2 Generic Names recommendation in [1]). [1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3 Suggested-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Suman Anna <s-anna@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20200903130015.21361-5-nm@ti.com
2020-09-07arm64: dts: ti: k3-am65*: Use generic gpio for node namesNishanth Menon
Use gpio@ naming for nodes following standard conventions of device tree (section 2.2.2 Generic Names recommendation in [1]). [1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3 Suggested-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200903130015.21361-4-nm@ti.com
2020-09-07arm64: dts: ti: k3-am65-main: Use lower case hexadecimalNishanth Menon
Device tree convention uses lower case a-f for hexadecimals. Fix the same. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200903130015.21361-3-nm@ti.com
2020-08-31arm64: dts: ti: k3-am65: restrict PCIe to Gen2 speedSekhar Nori
Per errata i2104 documented in AM65x device errata document (TI document number SPRZ452E, revised June 2019), Gen3 operation is not supported for both PCIe Root Complex and Endpoint modes of operation. See: https://www.ti.com/lit/er/sprz452e/sprz452e.pdf Restrict speed to Gen2 to address the errata. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200802165356.10285-1-nsekhar@ti.com
2020-08-31arm64: dts: ti: k3-am6: Add crypto accelarator nodeKeerthy
Add crypto accelarator node for supporting hardware crypto algorithms, including SHA1, SHA256, SHA512, AES, 3DES, and AEAD suites. [t-kristo@ti.com: Modifications based on introduction of yaml binding] Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200826082921.19143-2-t-kristo@ti.com
2020-08-16arm64: dts: k3-am65: Update the RM resource typesLokesh Vutla
Update the ringacc and udma dt nodes to use the latest RM resource types similar to the ones used in k3-j721e dt nodes. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200806074826.24607-14-lokeshvutla@ti.com
2020-08-16arm64: dts: k3-am65: ti-sci-inta/intr: Update to latest bindingsLokesh Vutla
Update the INTA and INTR dt nodes to the latest DT bindings. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200806074826.24607-13-lokeshvutla@ti.com
2020-07-17arm64: dts: ti: k3-am65/j721e-main: rename gic-its node to msi-controllerGrygorii Strashko
The preferable name for gic-its is msi-controller, so rename it to fix dtbs_check warning: k3-j721e-common-proc-board.dt.yaml: interrupt-controller@1800000: gic-its@1820000: False schema does not allow {'compatible': ['arm,gic-v3-its'], 'reg': [[0, 25296896, 0, 65536]], 'socionext,synquacer-pre-its': [[16777216, 4194304]], 'msi-controller': True, '#msi-cells': [[1]]} Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-07-17arm64: dts: ti: k3-*: Replace HTTP links with HTTPS onesAlexander A. Klimov
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-07-17arm64: dts: ti: k3-am65-main: Add support for sdhci1Faiz Abbas
Add support for the 2nd SDHCI controller on TI's AM654x SoCs. Although it supports upto SDR104 (100 MBps @ 200 MHz) speed mode, only enable support upto High Speed (25 MBps @ 50 MHz) for now. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-06-22arm64: dts: ti: k3-am654-main: Update otap-del-sel valuesFaiz Abbas
According to the latest AM65x Data Manual[1], a different output tap delay value is optimum for a given speed mode. Update these values. [1] http://www.ti.com/lit/gpn/am6526 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-06-04Merge tag 'arm-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM devicetree updates from Arnd Bergmann: "This is the set of device tree changes, mostly covering new hardware support, with 577 patches touching a little over 500 files. There are five new Arm SoCs supported in this release, all of them for existing SoC families: - Realtek RTD1195, RTD1395 and RTD1619 -- three SoCs used in both NAS devices and Android Set-top-box designs, along with the "Horseradish", "Lion Skin" and "Mjolnir" reference platforms; the Mele X1000 and Xnano X5 set-top-boxes and the Banana Pi BPi-M4 single-board computer. - Renesas RZ/G1H (r8a7742) -- a high-end 32-bit industrial SoC and the iW-RainboW-G21D-Qseven-RZG1H board/SoM - Rockchips RK3326 -- low-end 64-bit SoC along with the Odroid-GO Advance game console Newly added machines on already supported SoCs are: - AMLogic S905D based Smartlabs SML-5442TW TV box - AMLogic S905X3 based ODROID-C4 SBC - AMLogic S922XH based Beelink GT-King Pro TV box - Allwinner A20 based Olimex A20-OLinuXino-LIME-eMMC SBC - Aspeed ast2500 based BMCs in Facebook x86 "Yosemite V2" and YADRO OpenPower P9 "Nicole" - Marvell Kirkwood based Check Point L-50 router - Mediatek MT8173 based Elm/Hana Chromebook laptops - Microchip SAMA5D2 "Industrial Connectivity Platform" reference board - NXP i.MX8m based Beacon i.MX8m-Mini SoM development kit - Octavo OSDMP15x based Linux Automation MC-1 development board - Qualcomm SDM630 based Xiaomi Redmi Note 7 phone - Realtek RTD1295 based Xnano X5 TV Box - STMicroelectronics STM32MP1 based Stinger96 single-board computer and IoT Box - Samsung Exynos4210 based based Samsung Galaxy S2 phone - Socionext Uniphier based Akebi96 SBC - TI Keystone based K2G Evaluation board - TI am5729 based Beaglebone-AI development board Include device descriptions for additional hardware support in existing SoCs and machines based on all major SoC platforms: - AMlogic Meson - Allwinner sunxi - Arm Juno/VFP/Vexpress/Integrator - Broadcom bcm283x/bcm2711 - Hisilicon hi6220 - Marvell EBU - Mediatek MT27xx, MT76xx, MT81xx and MT67xx - Microchip SAMA5D2 - NXP i.MX6/i.MX7/i.MX8 and Layerscape - Nvidia Tegra - Qualcomm Snapdragon - Renesas r8a77961, r8a7791 - Rockchips RK32xx/RK33xx - ST-Ericsson ux500 - STMicroelectronics SMT32 - Samsung Exynos and S5PV210 - Socionext Uniphier - TI OMAP5/DRA7 and Keystone" * tag 'arm-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (564 commits) ARM: dts: keystone: Rename "msmram" node to "sram" arm: dts: mt2712: add uart APDMA to device tree arm64: dts: mt8183: add mmc node arm64: dts: mt2712: add ethernet device node arm64: tegra: Make the RTC a wakeup source on Jetson Nano and TX1 ARM: dts: mmp3: Add the fifth SD HCI ARM: dts: berlin*: Fix up the SDHCI node names ARM: dts: mmp3: Fix USB & USB PHY node names ARM: dts: mmp3: Fix L2 cache controller node name ARM: dts: mmp*: Fix up encoding of the /rtc interrupts property ARM: dts: pxa*: Fix up encoding of the /rtc interrupts property ARM: dts: pxa910: Fix the gpio interrupt cell number ARM: dts: pxa3xx: Fix up encoding of the /gpio interrupts property ARM: dts: pxa168: Fix the gpio interrupt cell number ARM: dts: pxa168: Add missing address/size cells to i2c nodes ARM: dts: dove: Fix interrupt controller node name ARM: dts: kirkwood: Fix interrupt controller node name arm64: dts: Add SC9863A emmc and sd card nodes arm64: dts: Add SC9863A clock nodes arm64: dts: mt6358: add PMIC MT6358 related nodes ...
2020-05-04arm64: dts: ti: k3-am65-main: add main navss cpts nodeGrygorii Strashko
Add DT node for Main NAVSS CPTS module. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-27arm64: dts: ti: k3-am65-main: Add ehrpwm nodesVignesh Raghavendra
Add DT nodes for all ehrpwm instances present on AM654 EVM. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-04-27arm64: dts: ti: am654: Add DSS nodeJyri Sarha
Add DSS node to k3-am65-main.dtsi with labels for board specific support and syscon node for oldi-io-ctrl. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-19arm64: dts: ti: k3-am65-main: Add DMA entries for main_spi0Vignesh Raghavendra
Add DMA entry for main_spi0, that has SPI flash connected, for better throughput and reduced CPU load. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-19arm64: dts: ti: k3-am65: Add clocks to dwc3 nodesDave Gerlach
The TI sci-clk driver can scan the DT for all clocks provided by system firmware and does this by checking the clocks property of all nodes, so we must add this to the dwc3 nodes so USB clocks are available. Without this USB does not work with latest system firmware i.e. [ 1.714662] clk: couldn't get parent clock 0 for /interconnect@100000/dwc3@4020000 Fixes: cc54a99464ccd ("arm64: dts: ti: k3-am6: add USB suppor") Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Cc: stable@kernel.org Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-01-24arm64: dts: ti: k3-am65-main Add CAL nodeBenoit Parrot
Add CAL dtsi node for AM654 device. Including proper power-domains and clock properties. Signed-off-by: Benoit Parrot <bparrot@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-01-24arm64: dts: ti: k3-am654-main: Add McASP nodesPeter Ujfalusi
Add the nodes for McASP 0-2 and keep them disabled because several required properties are not present as they are board specific. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-01-24arm64: dts: ti: k3-am65: DMA supportPeter Ujfalusi
Add the ringacc and udmap nodes for main and mcu NAVSS. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-01-24arm64: dts: ti: k3-am65-main: Move secure proxy under cbass_main_navssPeter Ujfalusi
Secure proxy (NAVSS0_SEC_PROXY0) is part of the Navigator Subsystem. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-01-24arm64: dts: ti: k3-am65-main: Correct main NAVSS representationPeter Ujfalusi
NAVSS is a subsystem containing different IPs, it is not really a bus. Change the compatible from "simple-bus" to "simple-mfd" to reflect that. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-18arm64: dts: ti: k3-am65-main: Add mailbox cluster nodesSuman Anna
The AM65x Main NavSS block contains a Mailbox IP instance with multiple clusters. Each cluster is equivalent to an Mailbox IP instance on OMAP platforms. Add all the Mailbox clusters as their own nodes under the MAIN NavSS cbass_main_navss interconnect node instead of creating an almost empty parent node for the new K3 mailbox IP and the clusters as its child nodes. All these nodes are enabled by default in the base dtsi file, but any cluster that does not define any child sub-mailbox nodes should be disabled in the corresponding board dts files. NOTE: The NavSS only has a limited number of interrupts, so none of the interrupts generated by a Mailbox IP are added by default. Only the needed interrupts that are targeted towards the A53 GIC will have to be added later on in the board dts files alongside the corresponding sub-mailbox child nodes. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-08-29arm64: dts: ti: k3-am65-main: Fix gic-its node unit-addressSuman Anna
The gic-its node unit-address has an additional zero compared to the actual reg value. Fix it. Fixes: ea47eed33a3f ("arm64: dts: ti: Add Support for AM654 SoC") Reported-by: Robert Tivy <rtivy@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-08-29arm64: dts: ti: k3-am65-main: Add hwspinlock nodeSuman Anna
The Main NavSS block on AM65x SoCs contains a HwSpinlock IP instance that is similar to the IP on some OMAP SoCs. Add the DT node for this on AM65x SoCs. The node is present within the NavSS block, and is added as a child node under the cbass_main_navss interconnect node. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-08-29arm64: dts: ti: k3-am654: Update the power domain cellsLokesh Vutla
Update the power-domain cells to 2 and mark all devices as exclusive. Main uart 0 is the debug console for based boards and it is used by different software entities like u-boot, atf, linux. So just mark main_uart0 as shared device for base board. Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: k3-am6: Add PCIe Endpoint DT nodeKishon Vijay Abraham I
Add PCIe Endpoint DT node. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: k3-am6: Add PCIe Root Complex DT nodeKishon Vijay Abraham I
Add PCIe Root Complex DT node. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: k3-am6: Add SERDES DT nodeKishon Vijay Abraham I
Add DT node for SERDES0 and SERDES1. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: k3-am6: Add mux-controller DT node required for muxing SERDESKishon Vijay Abraham I
Add mux-controller DT node as a child node of scm_conf. This is required for muxing SERDES between USB, PCIe and ICSS2 SGMII. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: k3-am6: Add "socionext,synquacer-pre-its" property to gic_itsKishon Vijay Abraham I
GIC_ITS used in AM654 platform has the same configuration as that of GIC_ITS used in Socionext SoCs. Add "socionext,synquacer-pre-its" property to get PCI MSI working. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: am6-main: Add gpio nodesKeerthy
Add gpio0/1 nodes under main domain. They have 96 and 90 gpios respectively and all are capable of generating banked interrupts. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: k3-am654: Add interrupt controllers in main domainLokesh Vutla
Main domain in AM654 has the following interrupt controller instances: - Main Domain GPIO Interrupt router connected to gpio in main domain. - Under the Main Domain Navigator Subsystem(NAVSS) - Main Navss Interrupt Router connected to main navss inta and mailboxes. - Main Navss Interrupt Aggregator connected to main domain UDMASS Add DT nodes for the above three interrupt controllers available in main domain. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-02-15arm64: dts: ti: k3-am6: add USB supportRoger Quadros
Adds support for USB0 and USB1 instances on the AM6 SoC. USB0 is limited to high-speed for now. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-02-15arm64: dts: ti: am654: Add Main System Control Module nodeJyri Sarha
Main System control module support is added to the device tree to allow driver to access to their control module registers. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-02-15arm64: dts: ti: k3-am65: Add MSMC RAM nodeRoger Quadros
The AM65 SoC has 2MB MSMC RAM. Add this as a mmio-sram node so drivers can use it via genpool API. Following areas are marked reserved: - Lower 128KB for ATF - 64KB@0xf0000 for SYSFW - Upper 1MB for cache The reserved locations are subject to change at runtime by the bootloader. Cc: Nishanth Menon <nm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Andrew F. Davis <afd@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-02-01arm64: dts: ti: k3-am654: Add Support for eMMC host controllerFaiz Abbas
Add support for the Secure Digital Host Controller Interface (SDHCI) present on TI's AM654 SOCs. It is compatible with eMMC5.1 Host Specifications. Enable only upto HS200 speed mode. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14arm64: dts: ti: k3-am654: Add McSPI DT nodesVignesh R
There are 3 instances of McSPI in MCU domain and 4 instances in Main domain. Add DT nodes for all McSPI instances present on AM654 SoC. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14arm64: dts: ti: k3-am654: Populate power-domain property for UART nodesVignesh R
Populate power-domain property for UART nodes, this is required for Linux to enable UART clocks via PM calls. Without this UART instances not initialized by bootloader (like main_uart1) fails to work in Linux. Also, drop current-speed property from main_uart1 and main_uart2 nodes as these UARTs are not initialized before Linux boots up and current speed is unknown. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14arm64: dts: ti: k3-am65-main: Add ECAP PWM nodeVignesh R
Add DT entry for ECAP0 PWM node present in main domain Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14arm64: dts: ti: k3-am654-base-board: Add I2C nodesVignesh R
Add DT entries for I2C instances present in AM654 SoC. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14arm64: dts: ti: k3-am65: Add pinctrl regionsTero Kristo
Add pinctrl regions for the main and wkup mmr. The range for main pinctrl region contains a gap at offset 0x2e4, and because of this, the pinctrl range is split into two sections. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
2018-09-18arm64: dts: ti: am654: Add secure proxy instance for main domainNishanth Menon
Add secure proxy instance for Main domain Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-09-18arm64: dts: ti: am654: Add uart nodesNishanth Menon
Add uart nodes for AM654 device tree components. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-09-18arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of ↵Kishon Vijay Abraham I
interconnect to 2 AM65 has two PCIe controllers and each PCIe controller has '2' address spaces one within the 4GB address space of the SoC and the other above the 4GB address space of the SoC (cbass_main) in addition to the register space. The size of the address space above the 4GB SoC address space is 4GB. These address ranges will be used by CPU/DMA to access the PCIe address space. In order to represent the address space above the 4GB SoC address space and to represent the size of this address space as 4GB, change address-cells and size-cells of interconnect to 2. Since OSPI has similar need in MCU Domain Memory Map, change address-cells and size-cells of cbass_mcu interconnect also to 2. Fixes: ea47eed33a3fe3d919 ("arm64: dts: ti: Add Support for AM654 SoC") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Vignesh R <vigneshr@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-07-18arm64: dts: ti: Add Support for AM654 SoCNishanth Menon
The AM654 SoC is a lead device of the K3 Multicore SoC architecture platform, targeted for broad market and industrial control with aim to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Quad ARMv8 A53 cores split over two clusters * GICv3 compliant GIC500 * Configurable L3 Cache and IO-coherent architecture * Dual lock-step capable R5F uC for safety-critical applications * High data throughput capable distributed DMA architecture under NAVSS * Three Gigabit Industrial Communication Subsystems (ICSSG), each with dual PRUs and dual RTUs * Hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL * Centralized System Controller for Security, Power, and Resource management. * Dual ADCSS, eQEP/eCAP, eHRPWM, dual CAN-FD * Flash subsystem with OSPI and Hyperbus interfaces * Multimedia capability with CAL, DSS7-UL, SGX544, McASP * Peripheral connectivity including USB3, PCIE, MMC/SD, GPMC, I2C, SPI, GPIO See AM65x Technical Reference Manual (SPRUID7, April 2018) for further details: http://www.ti.com/lit/pdf/spruid7 NOTE: 1. AM654 is the first of the device variants, hence we introduce a generic am65.dtsi. 2. We indicate the proper bus topology, the ranges are elaborated in each bus segment instead of using the top level ranges to make sure that peripherals in each segment use the address space accurately. 3. Peripherals in each bus segment is maintained in a separate dtsi allowing for reuse in different bus segment representation from a different core such as R5. This is also the reason for maintaining a 1-1 address map in the ranges. 4. Cache descriptions follow the ARM64 standard description. Further tweaks may be necessary as we introduce more complex devices, but can be introduced in context of the device introduction. Reviewed-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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