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2023-12-15arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed modeBhavya Kapoor
DDR50 speed mode is enabled for MMCSD in J784s4 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for MMCSD High Speed DDR which is DDR50 speed mode for J784s4 SoC according to datasheet for J784s4. [+] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in J784s4 datasheet - https://www.ti.com/lit/ds/symlink/tda4vh-q1.pdf Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Reviewed-by: Judith Mendez <jm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20231201082045.790478-4-b-kapoor@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-15arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed modeBhavya Kapoor
DDR50 speed mode is enabled for MMCSD in J721s2 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for MMCSD High Speed DDR which is DDR50 speed mode for J721s2 SoC according to datasheet for J721s2. [+] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in J721s2 datasheet - https://www.ti.com/lit/ds/symlink/tda4vl-q1.pdf Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Reviewed-by: Judith Mendez <jm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20231201082045.790478-3-b-kapoor@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-15arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed modeBhavya Kapoor
DDR52 speed mode is enabled for eMMC in J7200 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for eMMC High Speed DDR which is DDR52 speed mode for J7200 SoC according to datasheet for J7200. [+] Refer to : section 7.9.5.16.1 MMCSD0 - eMMC Interface, in J7200 datasheet - https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Reviewed-by: Judith Mendez <jm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20231201082045.790478-2-b-kapoor@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-15arm64: dts: ti: k3-am6*: Add additional regs for DMA componentsVignesh Raghavendra
Add additional reg properties for BCDMA and PKTDMA nodes which are mostly used by bootloader components before Device Manager firmware services are available, in order to setup DMA transfers. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231213135138.929517-4-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-15arm64: dts: ti: k3-j7*: Add additional regs for DMA componentsManorit Chawdhry
Add additional reg properties for UDMA and RingAcc nodes which are mostly used by bootloader components before Device Manager firmware services are available, in order to setup DMA transfers. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231213135138.929517-3-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-15arm64: dts: ti: k3-am65: Add additional regs for DMA componentsManorit Chawdhry
Add additional reg properties for UDMA and RingAcc nodes which are mostly used by bootloader components before Device Manager firmware services are available, in order to setup DMA transfers. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231213135138.929517-2-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-13arm64: dts: ti: k3-am62-main: Add GPU device nodeSarah Walker
Add the Series AXE GPU node to the AM62 device tree. Tested-by: Alexander Sverdlin <alexander.sverdlin@siemens.com> Signed-off-by: Sarah Walker <sarah.walker@imgtec.com> Signed-off-by: Donald Robson <donald.robson@imgtec.com> Acked-by: Darren Etheridge <detheridge@ti.com> Link: https://lore.kernel.org/r/7088cc032374ae517191b1dadf5bb5f0440eac81.1701773390.git.donald.robson@imgtec.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-13arm64: dts: ti: k3-j721s2-evm: Add overlay for PCIE1 Endpoint ModeSiddharth Vadapalli
Add overlay to enable the PCIE1 instance of PCIe on J721S2-EVM in Endpoint mode of operation. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231211115535.1264353-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-13arm64: dts: ti: k3-j721e-evm: Add overlay for PCIE0 Endpoint ModeSiddharth Vadapalli
Add overlay to enable the PCIE0 instance of PCIe on J721E-EVM in Endpoint mode of operation. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231211115535.1264353-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-13arm64: dts: ti: k3-j721e-sk: Add TPS6594 family PMICsNeha Malcom Francis
This patch adds support for TPS6594 PMIC family on wakeup I2C0 bus. These devices provide regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20231208114919.3429562-7-n-francis@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-13arm64: dts: ti: k3-am69-sk: Add support for TPS6594 PMICNeha Malcom Francis
This patch adds support for TPS6594 PMIC on wkup I2C0 bus. This device provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20231208114919.3429562-6-n-francis@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-13arm64: dts: ti: k3-j784s4-evm: Add support for TPS6594 PMICJerome Neanne
This patch adds support for TPS6593 PMIC on wkup I2C0 bus. This device provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Jerome Neanne <jneanne@baylibre.com> Signed-off-by: Esteban Blanc <eblanc@baylibre.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20231208114919.3429562-5-n-francis@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-13arm64: dts: ti: k3-j721e-som-p0: Add TP6594 family PMICsJerome Neanne
This patch adds support for TPS6594 PMIC family on wakup I2C0 bus. Theses devices provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Jerome Neanne <jneanne@baylibre.com> Signed-off-by: Esteban Blanc <eblanc@baylibre.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20231208114919.3429562-4-n-francis@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-13arm64: dts: ti: k3-j721s2-som-p0: Add TP6594 family PMICsEsteban Blanc
This patch adds support for TPS6594 PMIC family on wakup I2C0 bus. Theses devices provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Esteban Blanc <eblanc@baylibre.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20231208114919.3429562-3-n-francis@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-13arm64: dts: ti: k3-j7200-som-p0: Add TP6594 family PMICsEsteban Blanc
This patch adds support for TPS6594 PMIC family on wakup I2C0 bus. Theses devices provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Esteban Blanc <eblanc@baylibre.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Reid Tonking <reidt@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20231208114919.3429562-2-n-francis@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-06arm64: dts: ti: Add verdin am62 mallow boardJoao Paulo Goncalves
Add Toradex Verdin AM62 Mallow carrier board support. Mallow is a low-cost carrier board in the Verdin family with a small form factor and build for volume production making it ideal for industrial and embedded applications. https://www.toradex.com/products/carrier-board/mallow-carrier-board Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20231205184605.35225-4-francesco@dolcini.it Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-06arm64: dts: ti: verdin-am62: Improve spi1 chip-select pinctrlJoao Paulo Goncalves
Verdin SPI_1 interface has a dedicated hardware controlled chip select that is currently configured in the same pinctrl group as MISO/MOSI/CLK, however it is possible that it can be used only as a standard GPIO be it a chip select or not. To maximize flexibility and avoid duplication in the carrier board dts files move the SPI_1 CS in a dedicated pinctrl and also adds an additional pinctrl to simplify using SPI_1 CS as a GPIO. Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20231205184605.35225-2-francesco@dolcini.it Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-06arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Remove HDMI Reset Line NameGarrett Giordano
The GPIO Expander has a line name defined as GPIO0_HDMI_RST. This line is no longer associated with the HDMI Reset so we removed it. Signed-off-by: Garrett Giordano <ggiordano@phytec.com> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20231204222811.2344460-3-ggiordano@phytec.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-06arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Add HDMI supportGarrett Giordano
The DSS outputs DPI signals via its second video port (VP2). The DPI output from DSS is 24 bits (RGB888) and is forwarded to an HDMI transmitter (SIL9022) on the board. Add pinmux for DSS DPI output and HDMI Interrupt. Add DT nodes for SIL9022 HDMI transmitter (TX), and the HDMI connector on the phyBOARD-Lyra. Additionally, connect the output of DSS (VP2) with input of the HDMI TX, and the output of HDMI TX to the input of the HDMI connector. Signed-off-by: Garrett Giordano <ggiordano@phytec.com> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20231204222811.2344460-2-ggiordano@phytec.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-06arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Lower I2C1 frequencyGarrett Giordano
The gpio-expander on i2c-1 has a maximum frequency of 100kHz. Update our main_i2c1 frequency to allow the nxp,pcf8574 gpio-expander to function properly. Signed-off-by: Garrett Giordano <ggiordano@phytec.com> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20231204222811.2344460-1-ggiordano@phytec.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-06arm64: dts: ti: phycore-am64: Add R5F DMA Region and MailboxesGarrett Giordano
Communication between the R5F subsystem and Linux takes place using DMA memory regions and mailboxes. Here we add DT nodes for the memory regions and mailboxes to facilitate communication between the R5 clusters and Linux as remoteproc will fail to start if no memory regions or mailboxes are provided. Fixes: c48ac0efe6d7 ("arm64: dts: ti: Add support for phyBOARD-Electra-AM642") Signed-off-by: Garrett Giordano <ggiordano@phytec.com> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20231204212304.1736306-1-ggiordano@phytec.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-05arm64: dts: ti: Use OF_ALL_DTBS for combined blobsJai Luthra
Combined dtb builds are only useful for making sure that the overlay applies cleanly on the base dtb. So we move all such combined blobs under a `dtb- +=` section that is only built when CONFIG_OF_ALL_DTBS is enabled. Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231201-csi_dts-v3-9-9f06f31080fe@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-05arm64: dts: ti: k3-am62x: Add overlay for IMX219Jai Luthra
RPi v2 Camera (IMX219) is an 8MP camera that can be used with SK-AM62A through the 22-pin CSI-RX connector. Same overlay can be used across SK-AM62* boards that have a 15/22-pin FFC connector, so we name it with the k3-am62x- prefix. Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231201-csi_dts-v3-8-9f06f31080fe@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-05arm64: dts: ti: k3-am62a7-sk: Enable camera peripheralsJai Luthra
Enable I2C-2 as it is used to control CSI based sensors. Also enable IO-EXP-2 as it controls the mux between different CSI-2 connectors. Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231201-csi_dts-v3-7-9f06f31080fe@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-05arm64: dts: ti: k3-am62x: Add overlays for OV5640Jai Luthra
Three different OV5640 modules are supported using the 15-pin FFC connector on SK-AM62: - Digilent PCam 5C - ALINX AN5641 - TEVI-OV5640-*-RPI The Digilent and ALINX modules supply a 12Mhz XCLK to the sensor, while the TEVI module supplies a 24Mhz XCLK, thus requiring a separate overlay. These overlays can be used on other boards of the SK-AM62* family that have a 15/22-pin FFC connector, so we name the overlays with the prefix k3-am62x-. Tested-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231201-csi_dts-v3-6-9f06f31080fe@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-05arm64: dts: ti: k3-am62x-sk: Enable camera peripheralsJai Luthra
CSI cameras are controlled using I2C, on SK-AM62 and derivative boards this is routed to I2C-2, so enable that bus. Specific sensor connected to this bus will be described in the DT overlay for each sensor. Tested-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231201-csi_dts-v3-5-9f06f31080fe@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-05arm64: dts: ti: k3-am625-beagleplay: Add overlays for OV5640Jai Luthra
Three different OV5640 modules are supported using the FFC connector on BeaglePlay: - Digilent PCam 5C - ALINX AN5641 - TEVI-OV5640-*-RPI The Digilent and ALINX modules supply a 12Mhz XCLK to the sensor, while the TEVI module supplies a 24Mhz XCLK, thus requiring a separate overlay. Reviewed-by: Andrew Davis <afd@ti.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231201-csi_dts-v3-4-9f06f31080fe@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-05arm64: dts: ti: k3-am62a-main: Enable CSI2-RXJai Luthra
Add nodes for Cadence DPHY, CSI2RX and TI's pixel-grabbing wrapper. AM62A uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231201-csi_dts-v3-3-9f06f31080fe@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-05arm64: dts: ti: k3-am62-main: Enable CSI2-RXJai Luthra
The CSI2RX subsystem can be used to capture video frames from CSI-2 cameras. Add nodes for the CSI core, SHIM layer, and the DPHY. Tested-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231201-csi_dts-v3-2-9f06f31080fe@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-05arm64: dts: ti: k3-am65: Add AM652 dtsi fileAndrew Davis
The AM652 is basically a AM654 but with 2 cores instead of 4. Add a DTSI file for AM652 matching AM654 except this core difference. This removes the need to remove the extra cores from AM654 manually in DT files for boards that use the AM652 variant. Do that for the IOT2050 boards here. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20231205162358.23904-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-04arm64: dts: ti: k3-am625-beagleplay: Use UART name in pinmux nameAndrew Davis
The main_uart0 may not always be the console, but it will always be the UART0 in MAIN domain. Name the pinmux node to match. This makes it consistent with all other TI SoC based boards. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231127193602.151499-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-04arm64: dts: ti: k3-am62a7-sk: Add interrupt support for IO ExpanderAradhya Bhatia
The Hot Plug Detect (HPD) signal for the HDMI display travels from the on-board HDMI connector, through the IO Expander 1, and finally to the main_gpio1 GPIO 23, of the SoC. Add interrupt information for the IO Expander 1 (exp1) along with the relevant pinmux. Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231108191652.1118155-1-a-bhatia1@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-04arm64: dts: ti: k3-am625-verdin: Enable Verdin UART2Parth Pancholi
Enable UART2 for AM62 based SOM's Verdin carrier boards Dahlia, Development and Yavia. Earlier Verdin UART2 was reserved by R5 DM firmware which can be now configured using boardcfg during U-boot compilation. In a default config, no one writes to this UART. Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20231121160436.1032364-1-parth105105@gmail.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-04arm64: dts: ti: k3-am62-main: Add gpio-ranges propertiesRonald Wahl
On the AM62 platform we have no single 1:1 relation regarding index of gpio and pin controller. Actually there are some linear ranges with small holes inbetween. These ranges can be represented with the gpio-ranges device tree property. They have been extracted manually from the AM62x datasheet (Table 6-1. Pin Attributes). Signed-off-by: Ronald Wahl <ronald.wahl@raritan.com> Link: https://lore.kernel.org/r/20231127112657.2692103-1-rwahl@gmx.de Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-04arm64: dts: ti: k3-am64: Enable SDHCI nodes at the board levelAndrew Davis
SDHCI nodes defined in the top-level AM64 SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117163339.89952-2-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-04arm64: dts: ti: k3-am65: Enable SDHCI nodes at the board levelAndrew Davis
SDHCI nodes defined in the top-level AM65 SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117163339.89952-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-04arm64: dts: ti: k3-am65: Add full compatible to dss-oldi-io-ctrl nodeAndrew Davis
This matches the binding for this register region which fixes a couple DTS check warnings. While here trim the leading 0s from the "reg" definition. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com> Link: https://lore.kernel.org/r/20231117141433.9461-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-04arm64: dts: ti: k3-j784s4: Add chipid node to wkup_conf busAndrew Davis
Like in other K3 SoCs the chipid register is inside the wakeup configuration space. Move the chipid node under a new bus to better represent this topology and match other similar SoCs. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117140910.8747-2-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-04arm64: dts: ti: k3-j721s2: Add chipid node to wkup_conf busAndrew Davis
Like in other K3 SoCs the chipid register is inside the wakeup configuration space. Move the chipid node under a new bus to better represent this topology and match other similar SoCs. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117140910.8747-3-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-04arm64: dts: ti: k3-j721e: Add chipid node to wkup_conf busAndrew Davis
Like in other K3 SoCs the chipid register is inside the wakeup configuration space. Move the chipid node under a new bus to better represent this topology and match other similar SoCs. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117140910.8747-5-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-04arm64: dts: ti: k3-j7200: Add chipid node to wkup_conf busAndrew Davis
Like in other K3 SoCs the chipid register is inside the wakeup configuration space. Move the chipid node under a new bus to better represent this topology and match other similar SoCs. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117140910.8747-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-04arm64: dts: ti: k3-am65: Add chipid node to wkup_conf busAndrew Davis
Like in other K3 SoCs the chipid register is inside the wakeup configuration space. Move the chipid node under a new bus to better represent this topology and match other similar SoCs. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117140910.8747-4-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-01arm64: dts: ti: k3-am68-sk-base-board: Add alias for MCU CPSW2GSiddharth Vadapalli
Add alias for the MCU CPSW2G port to enable Linux to fetch MAC Address for the port directly from U-Boot. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Link: https://lore.kernel.org/r/20231115085913.3585740-1-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-01arm64: dts: ti: iot2050: Add icssg-prueth nodes for PG2 devicesJan Kiszka
Add the required nodes to enable ICSSG SR2.0 based prueth networking. As the driver still needs to be extended for SR1.0 support, keep related nodes disabled on PG1 devices. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/565d31a5fd29c4dd0cf28e347049a1247a6e446c.1699087938.git.jan.kiszka@siemens.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-01arm64: dts: ti: iot2050: Refactor the m.2 and minipcie power pinSu Bao Cheng
Make the m.2 power control pin also available on miniPCIE variants. This can fix some miniPCIE card hang issue, by forcing a power on reset during boot. Signed-off-by: Baocheng Su <baocheng.su@siemens.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/8b2f8c1698421b8d0694eb337ad7ea2320d76aa6.1699087938.git.jan.kiszka@siemens.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-01arm64: dts: ti: iot2050: Definitions for runtime pinmuxingBenedikt Niedermayr
Add multiple device tree nodes in order to support runtime pinmuxing via debugfs. All nodes are added to the pinctrl device node, since they are now belonging to multiple interfaces now. Note: Pinconf is also handled by debugfs-pinmux. This is possible since pinconf and pinmux accessing the same 32-Bit register and setting the function mask to 32-Bit allows writes to the whole register. Signed-off-by: Benedikt Niedermayr <benedikt.niedermayr@siemens.com> [Jan: fix node name style] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/3f90f3e521758622aa9b10f030cf0de1e68e77a4.1699087938.git.jan.kiszka@siemens.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-01arm64: dts: ti: iot2050: Drop unused ecap0 PWMJan Kiszka
In fact, this was never used by the final device, only dates back to first prototypes. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/6131d44e0505ca3efbb9039e5f2b637a3e139312.1699087938.git.jan.kiszka@siemens.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-01arm64: dts: ti: iot2050: Re-add aliasesJan Kiszka
Lost while dropping them from the common dtsi. Fixes: ffc449e016e2 ("arm64: dts: ti: k3-am65: Drop aliases") Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/1edbc1b56ed4ff2256d7afb7db3cab4b3a423692.1699087938.git.jan.kiszka@siemens.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-01arm64: dts: ti: k3-am62x-sk-common: Mark mcu gpio and mcu_gpio_intr as reservedVignesh Raghavendra
These are typically under MCU Firmware usage. Hence mark them reserved. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20231110132508.3137454-3-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-01arm64: dts: ti: k3-am62p5-sk: Mark mcu gpio and mcu_gpio_intr as reservedVignesh Raghavendra
These are typically under MCU Firmware usage. Hence mark them reserved. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20231110132508.3137454-2-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
generated by cgit (git 2.34.1) at 2024-07-03 07:17:28 +0000