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2023-05-08arm64: dts: ti: add missing cache propertiesKrzysztof Kozlowski
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: k3-am6528-iot2050-basic-pg2.dtb: l3-cache0: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230421223143.115099-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am65: Drop aliasesNishanth Menon
iot boards have always defined their own aliases and with the base-board defining it's own aliases, there are no pending boards depending on common aliases defined in SoC level. aliases are meant to be defined appropriately based on the exposed interfaces at a board level, drop the aliases defined at SoC level. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-8-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am654-base-board: Add aliasesNishanth Menon
Introduce aliases compatible with the base definition, but focussed on the interfaces that have been exposed on the platform. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-7-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am654-base-board: Add board detect eepromNishanth Menon
Enable AT24CM01 on the base board using the corresponding compatible. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-6-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am654-base-board: Add missing PMICNishanth Menon
Add the missing vdd_mpu PMIC. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-5-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am654-base-board: Add VTT GPIO regulator for DDRNishanth Menon
Hold the DDR vtt regulator active for functionality. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-4-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am654-base-board: Rename regulator node nameNishanth Menon
Rename the regulator node names to the standard regulator-0.. numbers. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am654-base-board: Add missing pinmux wkup_uart, mcu_uart ↵Nishanth Menon
and mcu_i2c Many of the definitions depend on pinmux done by the bootloader. Be explicit about the pinmux for functionality and completeness. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am62a: Add watchdog nodesNishanth Menon
Add nodes for watchdogs: - 5 in main domain - 1 in MCU domain - 1 in wakeup domain Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230418012717.1230882-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am62a: Add general purpose timersNishanth Menon
Similar to commit 3308a31c507c ("arm64: dts: ti: k3-am62: Add general purpose timers for am62"), there are 12 general purpose timers on am62a7 split between 8 in main and 4 in mcu domains. The 4 in mcu domain do not have interrupts that are routable to a53. We configure the timers with the 25 MHz input clock by default as the 32.768 kHz clock may not be wired on the device. We leave the MCU domain timers clock mux unconfigured, and mark the MCU domain timers reserved. The MCU domain timers are likely reserved by the software for the ESM module. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230418012717.1230882-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-j721s2-common-proc-board: Drop bootargsNishanth Menon
Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230419141222.383567-6-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-j7200-common-proc-board: Drop bootargsNishanth Menon
Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230419141222.383567-5-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-j721e-*: Drop bootargsNishanth Menon
Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230419141222.383567-4-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am65*: Drop bootargsNishanth Menon
Drop bootargs from the dts. earlycon is a debug property that should be enabled only when debug is desired and not as default - see referenced link on discussion on this topic. Cc: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/20230419141222.383567-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am62x-sk-common: Drop bootargsNishanth Menon
Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230419141222.383567-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-sk|evm: Drop bootargs, add aliasesNishanth Menon
Drop bootargs and add aliases based on base pinout of SK as per [1] and evm per [2]. Indices chosen attempt to maintain some level of consistency with existing aliases. While at this, drop a extra EoL. While this patch could be split, it seems trivial to add additional cleanup steps. [1] https://www.ti.com/lit/df/sprr432/sprr432.pdf [2] https://www.ti.com/lit/zip/swrr171 Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-11-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-evm: Add VTT GPIO regulator for DDRNishanth Menon
Hold the DDR vtt regulator active for functionality. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-10-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-evm: Rename regulator node nameNishanth Menon
Rename the regulator node names to the standard regulator-0.. numbers. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-9-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-evm: Describe main_uart1 pinsNishanth Menon
Describe the main_uart1 pins even though it is a reserved node for hardware complete description. This is used by other users of device tree to help configure the SoC per board requirements. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-8-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-evm: Enable main_i2c0 and eepromNishanth Menon
Enable AT24CM01 on the base board using the corresponding compatible. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-7-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-sk: Rename regulator node nameNishanth Menon
Rename the regulator node names to the standard regulator-0.. numbers. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-6-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-sk: Describe main_uart1 pinsNishanth Menon
Describe the main_uart1 pins even though it is a reserved node for hardware complete description. This is used by other users of device tree to help configure the SoC per board requirements. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-5-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-sk: Enable main_i2c0 and eepromNishanth Menon
Enable AT24C512C on the base board. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-4-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-sk: Fix mmc1 pinmuxNishanth Menon
Fix the pinmux for pulldirection to get stable sdcard behavior. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am64: Add general purpose timersNishanth Menon
There are 11 general purpose timers on am64 that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional four timers in the MCU domain that do not have interrupts routable for Linux. We configure the timers with the 25 MHz input clock by default as the 32.768 kHz clock may not be wired on the device. We leave the MCU domain timers clock mux unconfigured, and mark the MCU domain timers reserved. The MCU domain timers are likely reserved by the software for the ESM module. Compared to am65, the timers on am64 do not have a dedicated IO mux for the timers. On am62, the timers have different interrupts, clocks and power domains compared to am65, and the MCU timers are at a different IO address. Compared to AM62, the AM64 times have different clocks and count in main domain are different as well. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-03-30arm64: dts: ti: k3-j784s4-evm: Add eMMC mmc0 supportApurva Nandan
Add support for eMMC connected to main sdhci0 instance. Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20230327083100.12587-1-a-nandan@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: Enable audio on SK-AM62(-LP)Jai Luthra
Add nodes for audio codec and sound card, enable the audio serializer (McASP1) under use from SK-AM62 E2 [1] onwards and update pinmux. Keep all audio related nodes in the common dtsi as they are exactly the same between SK-AM62 and SK-AM62-LP [2]. Link: https://www.ti.com/lit/zip/sprr448 [1] Link: https://www.ti.com/lit/zip/sprr471 [2] Signed-off-by: Jai Luthra <j-luthra@ti.com> Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com> Link: https://lore.kernel.org/r/20230313-mcasp_upstream-v10-2-94332149657a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-am62-main: Add McASP nodesJayesh Choudhary
Add the nodes for McASP 0-2. Use the audio-friendly 96MHz main_1_hsdivout6_clk as clock parent instead of the default 100Mhz main_2_hsdivout8_clk source. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230313-mcasp_upstream-v10-1-94332149657a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-j784s4: Add MCSPI nodesVaishnav Achath
J784S4 has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Keerthy <j-keerthy@ti.com> Link: https://lore.kernel.org/r/20230321082827.14274-5-vaishnav.a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-j721s2: Add MCSPI nodesVaishnav Achath
J721S2 has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Keerthy <j-keerthy@ti.com> Link: https://lore.kernel.org/r/20230321082827.14274-4-vaishnav.a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-j7200: Add MCSPI nodesVaishnav Achath
J7200 has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Keerthy <j-keerthy@ti.com> Link: https://lore.kernel.org/r/20230321082827.14274-3-vaishnav.a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-j721e: Add MCSPI nodesVaishnav Achath
J721E has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Co-developed-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20230321082827.14274-2-vaishnav.a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: ti: dts: Add support for AM62x LP SKAnand Gadiyar
The AM62x LP SK board is similar to the AM62x SK board, but has some not-so-minor changes that requires different device tree. The differences are mainly: - AM62x SoC in the AMC package that meets AECQ100 automotive standard. - LPDDR4 versus DDR4 on the AM62x SK. - TPS65219 PMIC instead of discrete regulators. - IO expander pin names are wired differently. - Second ethernet port is currently disabled as the boards do not have the part physically installed. - OSPI NAND vs OSPI NOR. - No WLAN chip instead a SDIO M.2 connector. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> [vigneshr@ti.com: Add PMIC node] Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230321-am62-lp-sk-v2-3-0a56e1694804@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: Refractor AM625 SK dtsAnand Gadiyar
To prepare for upcoming derivative boards based on the AM625 SK, refactor the dts file for this board into a common dtsi file that the derivative boards will inherit and retain only those parts that are different in the current dts file. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230321-am62-lp-sk-v2-2-0a56e1694804@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-am625-sk: Add ti,vbus-divider property to usbss1Dhruva Gole
The property "ti,vbus-divider" is needed for both usbss0 and usbss1 as both USB0 and USB1 have the same external voltage divider circuit. Fixes: 2d94dfc43885 ("arm64: dts: ti: k3-am625-sk: Add support for USB") Signed-off-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230328124315.123778-2-rogerq@kernel.org Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-am68-sk-base-board: Update IO EXP GPIO lines for Rev E2Sinthu Raja
Rev E2 of the AM68 SK baseboard has updated the GPIO IO expander pins functionality. To match the Rev E2 schematics, update existing IO expander GPIO line names and the corresponding node which uses the expansion(exp1) node. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Link: https://lore.kernel.org/r/20230315120934.16954-1-sinthu.raja@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: Add k3-am625-beagleplayRobert Nelson
BeagleBoard.org BeaglePlay is an easy to use, affordable open source hardware single board computer based on the Texas Instruments AM625 SoC that allows you to create connected devices that work even at long distances using IEEE 802.15.4g LR-WPAN and IEEE 802.3cg 10Base-T1L. Expansion is provided over open standards based mikroBUS, Grove and QWIIC headers among other interfaces. This board family can be identified by the 24c32 eeprom: [aa 55 33 ee 01 37 00 10 2e 00 42 45 41 47 4c 45 |.U3..7....BEAGLE|] [50 4c 41 59 2d 41 30 2d 00 00 30 32 30 30 37 38 |PLAY-A0-..020078|] https://beagleplay.org/ https://git.beagleboard.org/beagleplay/beagleplay Signed-off-by: Robert Nelson <robertcnelson@gmail.com> Reviewed-by: Andrew Davis <afd@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230316152143.2438928-3-nm@ti.com Co-developed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII modeSiddharth Vadapalli
The J7 Quad Port Add-On Ethernet Card for J7200 Common-Proc-Board supports QSGMII mode. Use the overlay to configure CPSW5G ports in QSGMII mode. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW5G ports to enable kernel to fetch MAC addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315062307.1612220-5-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: j7200-main: Add CPSW5G nodesSiddharth Vadapalli
TI's J7200 SoC has a 5 port Ethernet Switch instance with 4 external ports and 1 host port, referred to as CPSW5G. Add device-tree nodes for CPSW5G and disable it by default. Device-tree overlays will be used to enable it. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315062307.1612220-4-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII modeSiddharth Vadapalli
The J7 Quad Port Add-On Ethernet Card for J721E Common-Proc-Board supports QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315062307.1612220-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j721e: Add CPSW9G nodesSiddharth Vadapalli
TI's J721E SoC has a 9 port Ethernet Switch instance with 8 external ports and 1 host port, referred to as CPSW9G. Add device-tree nodes for CPSW9G and disable it by default. Device-tree overlays will be used to enable it. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315062307.1612220-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2GSiddharth Vadapalli
Add device tree support to enable MCU CPSW with J784S4 EVM. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315042548.1500528-1-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j721s2-common-proc-board: Add pinmux information for ADCBhavya Kapoor
J721s2 has two instances of 8 channel ADCs in MCU domain. Add pinmux information for both ADC nodes. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230316095146.498999-3-b-kapoor@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-am62: Add watchdog nodesJulien Panis
Add nodes for watchdogs : - 5 in main domain - 1 in MCU domain - 1 in wakeup domain Signed-off-by: Julien Panis <jpanis@baylibre.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230320165123.80561-3-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-am62-wakeup: Introduce RTC nodeNishanth Menon
Introduce digital RTC node in wakeup domain. Even though this has no specific battery backup supply, this on-chip RTC is used in cost-optimized board designs as a wakeup source. Reviewed-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230320165123.80561-2-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support for ADC nodesBhavya Kapoor
J721s2 has two instances of 8 channel ADCs in MCU domain. Add support for both ADC nodes. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230316095146.498999-2-b-kapoor@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j784s4-main: Enable crypto acceleratorJayesh Choudhary
Add the node for SA2UL to support hardware crypto algorithms, including SHA-1/256/512, AES, 3DES and AEAD suites. Add rng node for hardware random number generator. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230314152611.140969-3-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: Use local header for pinctrl register valuesNishanth Menon
The DTS uses hardware register values directly in pin controller pin configuration and not an abstraction of any form. These definitions were previously put in the bindings header to avoid code duplication and to provide some context meaning (name), but they do not fit the purpose of bindings. Store the constants in a header next to DTS and use them instead of bindings. Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Suggested-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/all/c4d53e9c-dac0-8ccc-dc86-faada324beba@linaro.org/ Link: https://lore.kernel.org/r/20230315155228.1566883-3-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j721e-sk: Remove firmware-name override for R5FAndrew Davis
The firmware name for this core should stay as the default name "j7-main-r5f0_0-fw". This is expected to by a symlink to the actual firmware file. If one wants to use a different firmware they should change where the symlink points. This is usually achieved with an update-alternative or other distro specific selection mechanisms. The actual selection is policy and does not belong in DT. Remove this name override. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230307180942.2719-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-am62a7: Correct L2 cache size to 512KBVignesh Raghavendra
Per AM62Ax SoC datasheet[0] L2 cache is 512KB. [0] https://www.ti.com/lit/gpn/am62a7 Page 1. Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230320044935.2512288-2-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
generated by cgit (git 2.34.1) at 2025-04-16 16:20:37 +0000