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path: root/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
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2024-01-22arm64: zynqmp: Rename i2c?-gpio to i2c?-gpio-grpMichal Simek
Anything ending with gpio/gpios is taken as gpio phande/description which is reported as the issue coming from gpio-consumer.yaml schema. That's why rename the gpio suffix to gpio-grp to avoid name collision. Link: https://lore.kernel.org/r/94f633e26b7b16cabddb8c7210c2e79208c364da.1704728353.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13arm64: xilinx: Put ethernet phys to mdio nodeMichal Simek
All zynqmp boards have been already described via mdio node that's why also convert zc1751. With using mdio node there is an option to add reset property for the whole mdio bus. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/dc228a27579b48f3e768fcb439d118b4a0f0ef5b.1695040866.git.michal.simek@amd.com
2023-07-10arm64: zynqmp: Fix open drain warning on ZynqMPManikanta Guntupalli
Mark both GPIO lines as GPIO_OPEN_DRAIN which is required by i2c-gpio DT binding. Similar change was done by commit 8df80c1801c9 ("ARM: dts: exynos: Convert to new i2c-gpio bindings"). Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/a0faf488dde310e1c1c1a676c371e223db6bdca6.1686227712.git.michal.simek@amd.com
2023-06-05arm64: zynqmp: Set qspi tx-buswidth to 4Amit Kumar Mahapatra
All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
2023-06-05arm64: zynqmp: Fix usb node drive strength and slew rateAshok Reddy Soma
As per design, all input/rx pins should have fast slew rate and 12mA drive strength. Rest all pins should be slow slew rate and 4mA drive strength. Fix usb nodes as per this and remove setting of slow slew rate for all the usb group pins. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/379071f44ceb27a0e32d74e13221640922d989d1.1684767562.git.michal.simek@amd.com
2023-06-05arm64: zynqmp: Switch to amd.com emailsMichal Simek
Update my and DPs email address to match current setup. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.1685443337.git.michal.simek@amd.com
2023-05-12arm64: zynqmp: Add mali-400 gpu node for zynqmpParth Gajjar
Add mali-400 gpu node for zynqmp. Enabled gpu node for xilinx boards. Signed-off-by: Parth Gajjar <parth.gajjar@amd.com> Signed-off-by: Vishal Sagar <vishal.sagar@amd.com> Link: https://lore.kernel.org/r/20230321070619.29440-3-parth.gajjar@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2021-09-13arm64: zynqmp: Enable xlnx,zynqmp-dwc3 driver for xilinx boardsMichal Simek
The commit 84770f028fab ("usb: dwc3: Add driver for Xilinx platforms") finally add proper support for Xilinx dwc3 driver. This patch is adding DT description for it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/640a3bc0dc3e32560d3e84c2f78b5ae561396eb0.1628244703.git.michal.simek@xilinx.com
2021-09-13arm64: zynqmp: Add psgtr description to zc1751 dc1 boardMichal Simek
Wire psgtr for zc1751 dc1 board. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/51d9a5e0aa26b0ea79b8823bf3d15f4e2542f927.1623684253.git.michal.simek@xilinx.com
2021-09-13arm64: zynqmp: Sync psgtr node location with zcu104-revAMichal Simek
zcu104-revA has node below pinctrl which is not the same on revC. Sync location for easier comparison. Also zc1751-dc1 is not using this position. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/4b691bab5ba83b5352d4669bd54bcdb8273b2156.1623684253.git.michal.simek@xilinx.com
2021-09-13arm64: zynqmp: Wire qspi on multiple boardsMichal Simek
Couple of boards have qspi on the board that's why enable controller and describe them. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/01a69ee6590245b5bee70a2553f6faac0d31ca76.1623684253.git.michal.simek@xilinx.com
2021-09-13arm64: zynqmp: Add note about UHS mode on some boardsMichal Simek
Add note about UHS mode and add no-1-8-v property to zc1751-dc1 board. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/462b95844e7aedb00768035913265d7af90c3b2f.1623684253.git.michal.simek@xilinx.com
2021-09-13arm64: zynqmp: Wire DP and DPDMA for dc1/dc4Michal Simek
Enable Display Port and Display Port DMA for zc1751 dc1 and dc4. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/dbbd212bcc587e835d6df2f91622f5baa124bff5.1623684253.git.michal.simek@xilinx.com
2021-09-13arm64: zynqmp: Add missing mio-bank properties to dc1 and dc5Michal Simek
Add missing mio-bank properties to zc1751 dc1 and dc5 boards. The same change was done by commit 63481699d6e3 ("arm64: dts: zynqmp: Add missing mio-bank properties to sdhcis"). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/2b2ab31639c706651dfd319f5b6bc59e68f111b6.1623684253.git.michal.simek@xilinx.com
2021-09-13arm64: zynqmp: Wire psgtr for zc1751-xm015Michal Simek
Add psgtr description for SATA and USB. Display Port could be also added but it wasn't tested yet. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/3fb11fdb9ade828fa174379515e45ba02bc17247.1623684253.git.michal.simek@xilinx.com
2021-09-13arm64: zynqmp: Add pinctrl description for all boardsMichal Simek
The commit 1dccb5ec0123 ("dt-bindings: pinctrl: Add binding for ZynqMP pinctrl driver") and commit 8b242ca700f8 ("pinctrl: Add Xilinx ZynqMP pinctrl driver support") add support for Xilinx ZynqMP pinctrl driver that's why describe pins configuration for current boards. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/d8bc42600da85f5a23d977d4b61e6528720573e5.1623684253.git.michal.simek@xilinx.com
2020-01-09arm64: zynqmp: Use ethernet-phy as node name for ethernet physMichal Simek
Ethernet phys based on devicetree specification should be using ethernet-phy@ node name instead of pure phy@. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-09arm64: dts: xilinx: Add the clock nodes for zynqmpRajan Vaja
Add clock nodes for zynqmp based on CCF. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-12-12arm64: zynqmp: Add dr_mode property to usb nodeAnurag Kumar Vulisha
This patch adds dr_mode property to the usb node for zynqmp boards. Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-08arm64: zynqmp: Add support for Xilinx zc1751Michal Simek
Xilinx zc1751 boards is used for silicon validation. Board can be extended with 5 FMCs/DCs cards to connect various IPs. Describe all these combinations. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org>
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