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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree changes for v5.17-rc1
The vast majority of this contains various updates and cleanups to the
Tegra device trees that will eventually help validate all of them using
the dt-schema infrastructure.
Another notable chunk of this contains additional Tegra234 support as
well as support for the new Jetson AGX Orin Developer Kit.
* tag 'tegra-for-5.17-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (47 commits)
arm64: tegra: Add host1x hotflush reset on Tegra210
arm64: tegra: Hook up MMC and BPMP to memory controller
arm64: tegra: Add memory controller on Tegra234
arm64: tegra: Add EMC general interrupt on Tegra194
arm64: tegra: Update SDMMC4 speeds for Tegra194
arm64: tegra: Add dma-coherent for Tegra194 VIC
arm64: tegra: Rename Ethernet PHY nodes
arm64: tegra: Remove unused only-1-8-v properties
arm64: tegra: Sort Tegra210 XUSB clocks correctly
arm64: tegra: Add missing TSEC properties on Tegra210
arm64: tegra: jetson-nano: Remove extra PLL power supplies for PCIe and XUSB
arm64: tegra: smaug: Remove extra PLL power supplies for XUSB
arm64: tegra: jetson-tx1: Remove extra PLL power supplies for PCIe and XUSB
arm64: tegra: Rename GPIO hog nodes to match schema
arm64: tegra: Remove unsupported regulator properties
arm64: tegra: Rename TCU node to "serial"
arm64: tegra: Remove undocumented Tegra194 PCIe "core_m" clock
arm64: tegra: Drop unused properties for Tegra194 PCIe
arm64: tegra: Fix Tegra194 HSP compatible string
arm64: tegra: Drop unsupported nvidia,lpdr property
...
Link: https://lore.kernel.org/r/20211217162253.1801077-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.17 (take two)
- Initial support for the R-Car S4-8 SoC on the Spider CPU and
BreakOut boards,
- MIPI DSI display support for the R-Car V3u SoC and the Falcon board
stack,
- Thermal and GPU support for the RZ/G2L SoC and the RZ/G2L SMARC EVK
development board,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: Fix pin controller node names
arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
arm64: dts: renesas: r9a07g044: Create thermal zone to support IPA
arm64: dts: renesas: r9a07g044: Add TSU node
arm64: dts: renesas: falcon-cpu: Add DSI display output
arm64: dts: renesas: r8a779a0: Add DSI encoders
arm64: dts: renesas: Add Renesas Spider boards support
arm64: dts: renesas: Add Renesas R8A779F0 SoC support
dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions
dt-bindings: power: Add r8a779f0 SYSC power domain definitions
arm64: dts: renesas: Fix thermal bindings
Link: https://lore.kernel.org/r/cover.1639736718.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Our usual round of DT patches for the 5.17 merge window, with:
- Introduction of the chassis-type property
- I2C, SPDIF support for the Tanix TX6
- Memory frequency scaling for the A64 and H5
- Hantro G2 support for the H6
- New Board: Tanix TX6 Mini
* tag 'sunxi-dt-for-5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: h6: Add Hantro G2 node
arm64: dts: allwinner: h6: tanix-tx6: Enable bluetooth
arm64: dts: allwinner: h6: tanix: Add MMC1 node
arm64: dts: allwinner: h6: Add Tanix TX6 mini dts
dt-bindings: arm: sunxi: Add Tanix TX6 mini
arm64: dts: allwinner: h6: tanix-tx6: Split to DT and DTSI
ARM: dts: sun8i: Adjust power key nodes
arm64: dts: allwinner: a64: Update MBUS node
ARM: dts: sunxi: h3/h5: Update MBUS node
dt-bindings: arm: sunxi: Add H5 MBUS compatible
dt-bindings: arm: sunxi: Expand MBUS binding
dt-bindings: clock: sunxi: Export CLK_DRAM for devfreq
dt-bindings: crypto: Add optional dma properties
ARM: dts: sun8i: h3: beelink-x2: Add GPIO CEC node
ARM: dts: sunxi: Add CEC clock to DW-HDMI
arm64: dts: allwinner: a64: Add CEC clock to HDMI
ARM: dts: sun8i: h3: beelink-x2: Sort nodes
arm64: dts: allwinner: h6: tanix-tx6: Add I2C node
arm64: dts: allwinner: h6: tanix-tx6: Add SPDIF
arm64: dts: allwinner: add 'chassis-type' property
Link: https://lore.kernel.org/r/ef385139-6fd4-42d2-9bfe-a4dda7ac76c9.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add the host1x memory client hotflush reset on Tegra210.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Align all pin controller node names with the expectations of the DT
bindings in Documentation/devicetree/bindings/pinctrl/pinctrl.yaml.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/09a09c8ac9cb1a11b859c1ab9d9eae84cfefb1bb.1639666967.git.geert+renesas@glider.be
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Use the interconnects property to hook up the MMC and BPMP to the memory
controller. This is needed to set the correct bus-level DMA mask, which
is a prerequisite for adding IOMMU support.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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This adds the memory controller and the embedded external memory
controller found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add the missing EMC general interrupt for the external memory controller
on Tegra194.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add required device-tree properties to populate all speed
modes supported by SDMMC4 instance of Tegra194 SDHCI controller.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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DMA operations for the Tegra194 Video Image Compositor (VIC) are
coherent and so populate the 'dma-coherent' property.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Name the Ethernet PHY device tree nodes as expected by the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The only-1-8-v property is not support by an DT schema, so drop it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add missing interrupts, clocks, clock-names, reset and reset-names
properties for the TSEC blocks found on Tegra210.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the PCIe and XUSB controller device
tree nodes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the XUSB controller device tree
node.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the PCIe and XUSB controller device
tree nodes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to
the DT schema. Rename all such nodes to allow validation to pass.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Remove the unsupported "regulator-disable-ramp-delay" properties which
ended up in various DTS files for some reason.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The TCU is basically a serial port (albeit a fancy one), so it should be
named "serial".
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The "core_m" clock is not documented in the Tegra194 PCIe device tree
bindings, so remove it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The num-viewport property is never used and can be dropped, whereas the
"iommus" property is not needed since we use "iommu-map-mask" and
"iommu-map" already.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The HSP instances on Tegra194 are not fully compatible with the version
found on Tegra186, so drop the fallback compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Tegra194 pinmux DT bindings do not define the nvidia,lpdr property,
so drop them from the device trees that have listed them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The standard "jedec," vendor prefix should be used for SPI NOR flash
chips. This allows the right DT schema to be picked for validation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Audio graph endpoints don't have a "reg" property, so they shouldn't
have a unit-address either.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4
MiB - 1. This was likely presumed to be the "limit" rather than length.
Fix it up.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The I2C controller found on Tegra186 is not fully compatible with the
Tegra210 version, so drop the fallback compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Child nodes of the TI INA3221 power monitor device tree node should be
called input@* according to the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The DT schema requires that nodes representing thermal zones include a
"-thermal" suffix in their name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The CML1 and PLL_E clocks are never explicitly used by the AHCI
controller found on Tegra132, so drop them from the corresponding device
tree node.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The I2C controller found on Tegra124 is not fully compatible with the
Tegra114 version, so drop the fallback compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the
EMC. While at it, add the missing "#interconnect-cells" properties to
the memory controller and external memory controller nodes. Also set the
"#reset-cells" property for the memory controller because it exports the
hotflush reset controls.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The TKE (time-keeping engine) found on Tegra132 is not backwards
compatible with the version found on Tegra20, so update the compatible
string list accordingly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Tegra PMC device tree bindings don't support the "#wake-cells" and
"nvidia,reset-gpio" properties, so remove them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The AS3722 pinmux device tree node doesn't have a "reg" property and
therefore must not have a unit-address, so drop it.
While at it, add missing unit-addresses for the charger and smart
battery IC's on the ChromeOS embedded controller's I2C tunnel bus.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add the
device tree node on Tegra186.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Regulators defined at the top level in device tree are no longer part of
a simple bus and therefore don't have a reg property. Nodes without a
reg property shouldn't have a unit-address either, so drop the unit
address from the node names. To ensure nodes aren't duplicated (in which
case they would end up merged in the final DTB), append the name of the
regulator to the node name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Clocks defined at the top level in device tree are no longer part of a
simple bus and therefore don't have a reg property. Nodes without a reg
property shouldn't have a unit-address either, so drop the unit address
from the node names. To ensure nodes aren't duplicated (in which case
they would end up merged in the final DTB), append the name of the clock
to the node name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The display controllers are attached to a separate ARM SMMU instance
that is dedicated to servicing isochronous memory clients. Add this ISO
instance of the ARM SMMU to device tree.
Please note that the display controllers are not hooked up to this SMMU
yet, because we are still missing a means to transition framebuffers
used by the bootloader to the kernel.
This based upon an initial patch by Thierry Reding <treding@nvidia.com>.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Populate the device-tree nodes for NVENC and NVJPG Host1x engines on
Tegra186 and Tegra194.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add support to enumerate SD in UHS mode on Tegra194. Add required
device-tree properties in SDMMC1 and SDMMC3 instances to enable dynamic
pad voltage switching and enumerate SD card in UHS-I modes.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Jetson AGX Orin Developer Kit is a continuation of the Jetson
Developer Kit line using the new NVIDIA Tegra234 (Orin) SoC.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each,
for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches
with each cluster having an additional 256 KiB unified L2 cache and a 2
MiB L3 cache.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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These two controllers expose general purpose I/O pins that can be used
to control or monitor a variety of signals.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add a device for TCU (Tegra Combined UART) used for serial console.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add missing properties to the eMMC controller, as required to use it on
actual hardware.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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On final Tegra234 systems, shared memory for communication with BPMP is
located at offset 0x70000 in SYSRAM.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The RTC device requires a clock. Add it.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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