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2025-04-08arm64: dts: qcom: sm6350: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-18-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08arm64: dts: qcom: sm6125: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-17-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08arm64: dts: qcom: sm6115: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-16-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08arm64: dts: qcom: sdm845: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-15-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08arm64: dts: qcom: sdm670: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-14-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08arm64: dts: qcom: sdm630: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-13-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08arm64: dts: qcom: sc8180x: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-12-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08arm64: dts: qcom: sc7180: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-11-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08arm64: dts: qcom: qcm2290: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-10-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08arm64: dts: qcom: msm8998: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-9-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08arm64: dts: qcom: msm8996: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-8-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08arm64: dts: qcom: msm8976: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-7-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08arm64: dts: qcom: msm8953: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-6-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08arm64: dts: qcom: msm8939: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-5-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08arm64: dts: qcom: msm8917: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-4-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08arm64: dts: qcom: msm8916: Use the header with DSI phy clock IDsKrzysztof Kozlowski
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-3-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-08Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds
Pull kvm fixes from Paolo Bonzini: "ARM: - Rework heuristics for resolving the fault IPA (HPFAR_EL2 v. re-walk stage-1 page tables) to align with the architecture. This avoids possibly taking an SEA at EL2 on the page table walk or using an architecturally UNKNOWN fault IPA - Use acquire/release semantics in the KVM FF-A proxy to avoid reading a stale value for the FF-A version - Fix KVM guest driver to match PV CPUID hypercall ABI - Use Inner Shareable Normal Write-Back mappings at stage-1 in KVM selftests, which is the only memory type for which atomic instructions are architecturally guaranteed to work s390: - Don't use %pK for debug printing and tracepoints x86: - Use a separate subclass when acquiring KVM's per-CPU posted interrupts wakeup lock in the scheduled out path, i.e. when adding a vCPU on the list of vCPUs to wake, to workaround a false positive deadlock. The schedule out code runs with a scheduler lock that the wakeup handler takes in the opposite order; but it does so with IRQs disabled and cannot run concurrently with a wakeup - Explicitly zero-initialize on-stack CPUID unions - Allow building irqbypass.ko as as module when kvm.ko is a module - Wrap relatively expensive sanity check with KVM_PROVE_MMU - Acquire SRCU in KVM_GET_MP_STATE to protect guest memory accesses selftests: - Add more scenarios to the MONITOR/MWAIT test - Add option to rseq test to override /dev/cpu_dma_latency - Bring list of exit reasons up to date - Cleanup Makefile to list once tests that are valid on all architectures Other: - Documentation fixes" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (26 commits) KVM: arm64: Use acquire/release to communicate FF-A version negotiation KVM: arm64: selftests: Explicitly set the page attrs to Inner-Shareable KVM: arm64: selftests: Introduce and use hardware-definition macros KVM: VMX: Use separate subclasses for PI wakeup lock to squash false positive KVM: VMX: Assert that IRQs are disabled when putting vCPU on PI wakeup list KVM: x86: Explicitly zero-initialize on-stack CPUID unions KVM: Allow building irqbypass.ko as as module when kvm.ko is a module KVM: x86/mmu: Wrap sanity check on number of TDP MMU pages with KVM_PROVE_MMU KVM: selftests: Add option to rseq test to override /dev/cpu_dma_latency KVM: x86: Acquire SRCU in KVM_GET_MP_STATE to protect guest memory accesses Documentation: kvm: remove KVM_CAP_MIPS_TE Documentation: kvm: organize capabilities in the right section Documentation: kvm: fix some definition lists Documentation: kvm: drop "Capability" heading from capabilities Documentation: kvm: give correct name for KVM_CAP_SPAPR_MULTITCE Documentation: KVM: KVM_GET_SUPPORTED_CPUID now exposes TSC_DEADLINE selftests: kvm: list once tests that are valid on all architectures selftests: kvm: bring list of exit reasons up to date selftests: kvm: revamp MONITOR/MWAIT tests KVM: arm64: Don't translate FAR if invalid/unsafe ...
2025-04-08arm64: dts: fsd: Add Ethernet support for PERIC Block of FSD SoCSwathi K S
The FSD SoC contains two instances of Synopsys DWC QoS Ethernet IP, one in FSYS0 block and other in PERIC block. The ethernet interface is connected to a switch which is not managed by Linux. Adds device tree node for Ethernet in PERIC Block and enables the same for FSD platform. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com> Signed-off-by: Swathi K S <swathi.ks@samsung.com> Link: https://lore.kernel.org/r/20250307044904.59077-3-swathi.ks@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-04-08arm64: dts: fsd: Add Ethernet support for FSYS0 Block of FSD SoCSwathi K S
The FSD SoC contains two instances of Synopsys DWC QoS Ethernet IP, one in FSYS0 block and other in PERIC block. The ethernet interface is managed by a switch which is not managed by Linux. Adds device tree node for Ethernet in FSYS0 Block and enables the same for FSD platform. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com> Signed-off-by: Swathi K S <swathi.ks@samsung.com> Link: https://lore.kernel.org/r/20250307044904.59077-2-swathi.ks@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-04-08Merge tag 'kvmarm-fixes-6.15-1' of ↵Paolo Bonzini
https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm64: First batch of fixes for 6.15 - Rework heuristics for resolving the fault IPA (HPFAR_EL2 v. re-walk stage-1 page tables) to align with the architecture. This avoids possibly taking an SEA at EL2 on the page table walk or using an architecturally UNKNOWN fault IPA. - Use acquire/release semantics in the KVM FF-A proxy to avoid reading a stale value for the FF-A version. - Fix KVM guest driver to match PV CPUID hypercall ABI. - Use Inner Shareable Normal Write-Back mappings at stage-1 in KVM selftests, which is the only memory type for which atomic instructions are architecturally guaranteed to work.
2025-04-07KVM: arm64: Use acquire/release to communicate FF-A version negotiationWill Deacon
The pKVM FF-A proxy rejects FF-A requests other than FFA_VERSION until version negotiation is complete, which is signalled by setting the global 'has_version_negotiated' variable. To avoid excessive locking, this variable is checked directly from kvm_host_ffa_handler() in response to an FF-A call, but this can race against another CPU performing the negotiation and potentially lead to reading a torn value (incredibly unlikely for a 'bool') or problematic re-ordering of the accesses to 'has_version_negotiated' and 'hyp_ffa_version' whereby a stale version number could be read by __do_ffa_mem_xfer(). Use acquire/release primitives when writing 'has_version_negotiated' with the version lock held and when reading without the lock held. Cc: Sebastian Ene <sebastianene@google.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Quentin Perret <qperret@google.com> Cc: Oliver Upton <oliver.upton@linux.dev> Cc: Marc Zyngier <maz@kernel.org> Fixes: c9c012625e12 ("KVM: arm64: Trap FFA_VERSION host call in pKVM") Signed-off-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20250407152755.1041-1-will@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
2025-04-07Merge branch 'arm64-for-6.15' into arm64-for-6.16Bjorn Andersson
Changes queued for v6.15 would have had the potential to break bisectability and was therefor not accepted. Merge the whole set towards v6.16, as this is no longer a concern.
2025-04-07arm64: dts: broadcom: bcm2712-rpi-5-b: Enable PCIe DT nodesStanimir Varbanov
Enable pcie1 and pcie2 DT nodes. Pcie1 is used for the extension connector and pcie2 is used for RP1 south-bridge. Signed-off-by: Stanimir Varbanov <svarbanov@suse.de> Link: https://lore.kernel.org/r/20250120130119.671119-12-svarbanov@suse.de Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-04-07arm64: dts: broadcom: bcm2712: Add PCIe DT nodesStanimir Varbanov
Add PCIe devicetree nodes, plus needed reset and mip MSI-X controllers. Signed-off-by: Stanimir Varbanov <svarbanov@suse.de> Link: https://lore.kernel.org/r/20250120130119.671119-11-svarbanov@suse.de Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-04-07arm64: dts: allwinner: Add Allwinner A523 .dtsi fileAndre Przywara
The Allwinner A523, and its siblings A527 and T527, which share the same die, are a new family of SoCs introduced in 2023. They features eight Arm Cortex-A55 cores, and, among the other usual peripherals, a PCIe and USB 3.0 controller. Add the basic SoC devicetree .dtsi for the chip, describing the fundamental peripherals: the cores, GIC, timer, RTC, CCU and pinctrl. Also some other peripherals are fully compatible with previous IP, so add the USB and MMC nodes as well. The other peripherals will be added in the future, once we understand their compatibility and DT requirements. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307005712.16828-9-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-04-07arm64: dts: microchip: sparx5: Fix CPU node "enable-method" property ↵Rob Herring (Arm)
dependencies The "spin-table" enable-method requires "cpu-release-addr" property, so add a dummy entry. It is assumed the bootloader will fill in the correct values. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Daniel Machon <daniel.machon@microchip.com> Tested-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-04-07arm64: dts: renesas: Remove undocumented compatible micron,mt25qu512aBiju Das
Remove undocumented compatible micron,mt25qu512a. This fixes the dtbs warning: failed to match any schema with compatible: ['micron,mt25qu512a', 'jedec,spi-nor'] Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250309184326.75452-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-07arm64: dts: renesas: r8a779f4: Add UFS tuning parameters in E-FUSEGeert Uytterhoeven
Describe the location in the E-FUSE block of the PLL and AFE tuning parameters for the Universal Flash Storage controller. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/3e4fca228eb049d54a1ae520104558505dbdf803.1741179629.git.geert+renesas@glider.be
2025-04-07arm64: dts: renesas: r9a09g047: Add ICU nodeBiju Das
Add interrupt control node to RZ/G3E ("R9A09G047") SoC DTSI and add icu as interrupt-parent of pincontrol. Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250207113653.21641-13-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-07arm64: dts: renesas: r9a09g047e57-smarc: Enable SDHI1Biju Das
Enable SDHI1 on the RZ/G3E SMARC EVK platform using gpio regulator for voltage switching. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250206134047.67866-9-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-07arm64: dts: renesas: rzg3e-smarc-som: Add support to enable SD on SDHI0Biju Das
Add support for enabling SD on SDHI0 on RZ/G3E SMARC SoM. It is enabled by setting the macro SW_SD0_DEV_SEL to 1 in board DTS and setting the switch SYS.1 to ON position on the SoM. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250206134047.67866-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-07arm64: dts: renesas: rzg3e-smarc-som: Enable SDHI{0,2}Biju Das
Enable eMMC on SDHI0 and SD on SDHI2 on RZ/G3E SMARC SoM. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250206134047.67866-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-07arm64: dts: renesas: r9a09g057: Add support for enabling SDHI internal regulatorBiju Das
Add support for enabling SDHI internal regulator, by overriding the status on the board DTS, when needed. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/20250206134047.67866-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-07arm64: dts: renesas: r9a09g047: Add SDHI0-SDHI2 nodesBiju Das
Add SDHI0-SDHI2 nodes to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/20250206134047.67866-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-07arm64: dts: rockchip: Enable HDMI audio output for RK3588 Tiger HaikouQuentin Schulz
HDMI audio is available on the RK3588 Tiger Haikou HDMI TX port, so let's enable it. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250317-tsd-rk3588-hdmi-audio-v1-2-0b8ceb9597a6@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-07arm64: dts: rockchip: Enable HDMI audio output for RK3588 JaguarQuentin Schulz
HDMI audio is available on the RK3588 Jaguar HDMI TX port, so let's enable it. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250317-tsd-rk3588-hdmi-audio-v1-1-0b8ceb9597a6@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-07arm64: dts: rockchip: Enable HDMI ports on ArmSoM W3Jianfeng Liu
Enable the two HDMI ports on ArmSoM W3. And audio output of these two ports are also enabled. Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com> Link: https://lore.kernel.org/r/20250317163240.3083908-1-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-07arm64: dts: rockchip: aliase sdhci as mmc0 for rk3566 box demoAndy Yan
Follow most others rk356x based boards, and u-boot only use mmc0/1 as mmc boot targets, so aliase sdhci as mmc0. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> [demo-board only used internally by Rockchip, so changing the alias order does not affect public users] Link: https://lore.kernel.org/r/20241221104920.4193034-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-07arm64: dts: rockchip: Add gmac phy reset GPIO to QNAP TS433Uwe Kleine-König
While looking through the vendor U-Boot code Heiko spotted that a SoC GPIO is connected to the ethernet phy's reset pin. Add the respective reset-gpios property with pinmuxing for the GPIO to the phy node. Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/49f66206fccc714a8745b9ac35247615ad5cc369.1742331667.git.ukleinek@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-07arm64: dts: rockchip: Correct gmac phy address on QNAP TS433Uwe Kleine-König
The Motorcomm Phy can be talked to on mdio broadcast address 0, but the actuall address is 3. Adapt the reg property and node name accordingly. Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/6b8ef7e37e646f4cd399ceb2f46017644d76da9d.1742331667.git.ukleinek@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-07arm64: dts: rockchip: enable HDMI sound on FriendlyElec NanoPC-T6Marcin Juszkiewicz
We have both video outputs showing pixels, time to play some noise. Signed-off-by: Marcin Juszkiewicz <mjuszkiewicz@redhat.com> Link: https://lore.kernel.org/r/20250325-nanopc-t6-hdmi-v1-2-299a2ed45878@redhat.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-07arm64: dts: rockchip: enable HDMI1 on FriendlyElec NanoPC-T6Marcin Juszkiewicz
Time to get second video output working. Signed-off-by: Marcin Juszkiewicz <mjuszkiewicz@redhat.com> Link: https://lore.kernel.org/r/20250325-nanopc-t6-hdmi-v1-1-299a2ed45878@redhat.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-07arm64: dts: rockchip: Enable ufshc on rk3576 evb1 boardShawn Lin
RK3576 evb1 board supports UFS, so enable it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Link: https://lore.kernel.org/r/1741180586-140422-1-git-send-email-shawn.lin@rock-chips.com [the core device node went into the driver tree, hence this being later] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-07arm64: dts: rockchip: change rng reset id back to its constant valueHeiko Stuebner
With the binding header now providing the SCMI_SRST_H_TRNG_NS constant, switch back to it from the temporary numeric value. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-07arm64: dts: rockchip: Add pinmuxing for eMMC on QNAP TS433Uwe Kleine-König
Until now the emmc worked when booting because the bootrom set up the pin config correctly to load the initial bootloader from it. So when the kernel started it "just" reused this setup but never made sure it was actually correct. This then breaks when the system is started via some other means, like downloading the initial bootloader via the bootrom usb download. With actual emmc pin-config added, barebox is able to access the eMMC even when booted via USB. Fixes: 9da1c0327d58 ("arm64: dts: rockchip: Add basic support for QNAP TS-433") Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org> [refined commit message to explain that we're currently just running on bootom-goodwill] Link: https://lore.kernel.org/r/20250319113138.125192-2-uwe@kleine-koenig.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-07arm64: dts: rockchip: Remove overdrive-mode OPPs from RK3588J SoC dtsiDragan Simic
The differences in the vendor-approved CPU and GPU OPPs for the standard Rockchip RK3588 variant [1] and the industrial Rockchip RK3588J variant [2] come from the latter, presumably, supporting an extended temperature range that's usually associated with industrial applications, despite the two SoC variant datasheets specifying the same upper limit for the allowed ambient temperature for both variants. However, the lower temperature limit is specified much lower for the RK3588J variant. [1][2] To be on the safe side and to ensure maximum longevity of the RK3588J SoCs, only the CPU and GPU OPPs that are declared by the vendor to be always safe for this SoC variant may be provided. As explained by the vendor [3] and according to the RK3588J datasheet, [2] higher-frequency/higher-voltage CPU and GPU OPPs can be used as well, but at the risk of reducing the SoC lifetime expectancy. Presumably, using the higher OPPs may be safe only when not enjoying the assumed extended temperature range that the RK3588J, as an SoC variant targeted specifically at higher-temperature, industrial applications, is made (or binned) for. Anyone able to keep their RK3588J-based board outside the above-presumed extended temperature range at all times, and willing to take the associated risk of possibly reducing the SoC lifetime expectancy, is free to apply a DT overlay that adds the higher CPU and GPU OPPs. With all this and the downstream RK3588(J) DT definitions [4][5] in mind, let's delete the RK3588J CPU and GPU OPPs that are not considered belonging to the normal operation mode for this SoC variant. To quote the RK3588J datasheet [2], "normal mode means the chipset works under safety voltage and frequency; for the industrial environment, highly recommend to keep in normal mode, the lifetime is reasonably guaranteed", while "overdrive mode brings higher frequency, and the voltage will increase accordingly; under the overdrive mode for a long time, the chipset may shorten the lifetime, especially in high-temperature condition". To sum the RK3588J datasheet [2] and the vendor-provided DTs up, [4][5] the maximum allowed CPU core, GPU and NPU frequencies are as follows: IP core | Normal mode | Overdrive mode ------------+-------------+---------------- Cortex-A55 | 1,296 MHz | 1,704 MHz Cortex-A76 | 1,608 MHz | 2,016 MHz GPU | 700 MHz | 850 MHz NPU | 800 MHz | 950 MHz Unfortunately, when it comes to the actual voltages for the RK3588J CPU and GPU OPPs, there's a discrepancy between the RK3588J datasheet [2] and the downstream kernel code. [4][5] The RK3588J datasheet states that "the max. working voltage of CPU/GPU/NPU is 0.75 V under the normal mode", while the downstream kernel code actually allows voltage ranges that go up to 0.95 V, which is still within the voltage range allowed by the datasheet. However, the RK3588J datasheet also tells us to "strictly refer to the software configuration of SDK and the hardware reference design", so let's embrace the voltage ranges provided by the downstream kernel code, which also prevents the undesirable theoretical outcome of ending up with no usable OPPs on a particular board, as a result of the board's voltage regulator(s) being unable to deliver the exact voltages, for whatever reason. The above-described voltage ranges for the RK3588J CPU OPPs remain taken from the downstream kernel code [4][5] by picking the highest, worst-bin values, which ensure that all RK3588J bins will work reliably. Yes, with some power inevitably wasted as unnecessarily generated heat, but the reliability is paramount, together with the longevity. This deficiency may be revisited separately at some point in the future. The provided RK3588J CPU OPPs follow the slightly debatable "provide only the highest-frequency OPP from the same-voltage group" approach that's been established earlier, [6] as a result of the "same-voltage, lower-frequency" OPPs being considered inefficient from the IPA governor's standpoint, which may also be revisited separately at some point in the future. [1] https://wiki.friendlyelec.com/wiki/images/e/ee/Rockchip_RK3588_Datasheet_V1.6-20231016.pdf [2] https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403201054_Rockchip-RK3588J_C22364189.pdf [3] https://lore.kernel.org/linux-rockchip/e55125ed-64fb-455e-b1e4-cebe2cf006e4@cherry.de/T/#u [4] https://raw.githubusercontent.com/rockchip-linux/kernel/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi [5] https://raw.githubusercontent.com/rockchip-linux/kernel/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588j.dtsi [6] https://lore.kernel.org/all/20240229-rk-dts-additions-v3-5-6afe8473a631@gmail.com/ Fixes: 667885a68658 ("arm64: dts: rockchip: Add OPP data for CPU cores on RK3588j") Fixes: a7b2070505a2 ("arm64: dts: rockchip: Split GPU OPPs of RK3588 and RK3588j") Cc: stable@vger.kernel.org Cc: Heiko Stuebner <heiko@sntech.de> Cc: Alexey Charkov <alchark@gmail.com> Helped-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/eeec0d30d79b019d111b3f0aa2456e69896b2caa.1742813866.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-07arm64: dts: rockchip: Allow Turing RK1 cooling fan to spin downSam Edwards
The RK3588 thermal sensor driver only receives interrupts when a higher-temperature threshold is crossed; it cannot notify when the sensor cools back off. As a result, the driver must poll for temperature changes to detect when the conditions for a thermal trip are no longer met. However, it only does so if the DT enables polling. Before this patch, the RK1 DT did not enable polling, causing the fan to continue running at the speed corresponding to the highest temperature reached. Follow suit with similar RK3588 boards by setting a polling-delay of 1000ms, enabling the driver to detect when the sensor cools back off, allowing the fan speed to decrease as appropriate. Fixes: 7c8ec5e6b9d6 ("arm64: dts: rockchip: Enable automatic fan control on Turing RK1") Cc: stable@kernel.org # v6.13+ Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/20250329165017.3885-1-CFSworks@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-07crypto: arm64/chacha - remove the skcipher algorithmsEric Biggers
Since crypto/chacha.c now registers chacha20-$(ARCH), xchacha20-$(ARCH), and xchacha12-$(ARCH) skcipher algorithms that use the architecture's ChaCha and HChaCha library functions, individual architectures no longer need to do the same. Therefore, remove the redundant skcipher algorithms and leave just the library functions. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-07crypto: chacha - centralize the skcipher wrappers for arch codeEric Biggers
Following the example of the crc32 and crc32c code, make the crypto subsystem register both generic and architecture-optimized chacha20, xchacha20, and xchacha12 skcipher algorithms, all implemented on top of the appropriate library functions. This eliminates the need for every architecture to implement the same skcipher glue code. To register the architecture-optimized skciphers only when architecture-optimized code is actually being used, add a function chacha_is_arch_optimized() and make each arch implement it. Change each architecture's ChaCha module_init function to arch_initcall so that the CPU feature detection is guaranteed to run before chacha_is_arch_optimized() gets called by crypto/chacha.c. In the case of s390, remove the CPU feature based module autoloading, which is no longer needed since the module just gets pulled in via function linkage. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-05Merge tag 'kbuild-v6.15' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild Pull Kbuild updates from Masahiro Yamada: - Improve performance in gendwarfksyms - Remove deprecated EXTRA_*FLAGS and KBUILD_ENABLE_EXTRA_GCC_CHECKS - Support CONFIG_HEADERS_INSTALL for ARCH=um - Use more relative paths to sources files for better reproducibility - Support the loong64 Debian architecture - Add Kbuild bash completion - Introduce intermediate vmlinux.unstripped for architectures that need static relocations to be stripped from the final vmlinux - Fix versioning in Debian packages for -rc releases - Treat missing MODULE_DESCRIPTION() as an error - Convert Nios2 Makefiles to use the generic rule for built-in DTB - Add debuginfo support to the RPM package * tag 'kbuild-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild: (40 commits) kbuild: rpm-pkg: build a debuginfo RPM kconfig: merge_config: use an empty file as initfile nios2: migrate to the generic rule for built-in DTB rust: kbuild: skip `--remap-path-prefix` for `rustdoc` kbuild: pacman-pkg: hardcode module installation path kbuild: deb-pkg: don't set KBUILD_BUILD_VERSION unconditionally modpost: require a MODULE_DESCRIPTION() kbuild: make all file references relative to source root x86: drop unnecessary prefix map configuration kbuild: deb-pkg: add comment about future removal of KDEB_COMPRESS kbuild: Add a help message for "headers" kbuild: deb-pkg: remove "version" variable in mkdebian kbuild: deb-pkg: fix versioning for -rc releases Documentation/kbuild: Fix indentation in modules.rst example x86: Get rid of Makefile.postlink kbuild: Create intermediate vmlinux build with relocations preserved kbuild: Introduce Kconfig symbol for linking vmlinux with relocations kbuild: link-vmlinux.sh: Make output file name configurable kbuild: do not generate .tmp_vmlinux*.map when CONFIG_VMLINUX_MAP=y Revert "kheaders: Ignore silly-rename files" ...
generated by cgit (git 2.34.1) at 2025-10-02 02:52:44 +0000