| Age | Commit message (Expand) | Author |
|---|
| 2016-05-13 | MIPS: Add and use watch register field definitions | James Hogan |
| 2016-05-13 | MIPS: Add and use CAUSEF_WP definition | James Hogan |
| 2016-05-13 | MIPS: Detect MIPSr6 Virtual Processor support | Paul Burton |
| 2016-01-24 | MIPS: Update trap codes | James Hogan |
| 2016-01-24 | MIPS: Move Cause.ExcCode trap codes to mipsregs.h | James Hogan |
| 2016-01-24 | MIPS: Move definition of DC bit to mipsregs.h | James Hogan |
| 2015-11-11 | MIPS: Tidy EntryLo bit definitions, add PFN | Paul Burton |
| 2015-11-11 | MIPS: CPS: Early debug using an ns16550-compatible UART | Paul Burton |
| 2015-11-11 | MIPS: Fix duplicate CP0_* definitions. | James Hogan |
| 2015-09-22 | MIPS: cpu-features: Add cpu_has_ftlb | James Hogan |
| 2015-09-03 | MIPS: Rearrange ENTRYLO field definitions | James Hogan |
| 2015-09-03 | MIPS: Treat CP1 control registers as unsigned ints. | Ralf Baechle |
| 2015-09-03 | MIPS: Use unsigned int when reading CP0 registers | Chris Packham |
| 2015-08-26 | MIPS: Set up FTLB probability for I6400 | Markos Chandras |
| 2015-06-21 | MIPS: R12000: Enable branch prediction global history | Joshua Kinard |
| 2015-06-21 | MIPS: mipsregs.h: Add EntryLo bit definitions | James Hogan |
| 2015-04-08 | MIPS: math-emu: Define IEEE 754-2008 feature control bits | Maciej W. Rozycki |
| 2015-04-08 | MIPS: math-emu: Implement the FCCR, FEXR and FENR registers | Maciej W. Rozycki |
| 2015-04-08 | MIPS: mipsregs.h: Reindent CP0 Cause macros | Maciej W. Rozycki |
| 2015-04-08 | MIPS: mipsregs.h: Move TX39 macros out of the way | Maciej W. Rozycki |
| 2015-04-08 | MIPS: mipsregs.h: Reorder CP1 macro definitions | Maciej W. Rozycki |
| 2015-04-08 | MIPS: mipsregs.h: Remove broken comments | Maciej W. Rozycki |
| 2015-03-31 | MIPS: Add architectural FDC IRQ fields | James Hogan |
| 2015-03-31 | MIPS: Add arch CDMM definitions and probing | James Hogan |
| 2015-02-21 | Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus | Linus Torvalds |
| 2015-02-20 | MIPS: Add set/clear CP0 macros for PageGrain register | Steven J. Hill |
| 2015-02-17 | MIPS: asm: mipsregs: Add support for the LLADDR register | Markos Chandras |
| 2015-02-17 | MIPS: Add LLB bit and related feature for the Config 5 CP0 register | Markos Chandras |
| 2015-01-30 | MIPS: mipsregs.h: Add write_32bit_cp1_register() | James Hogan |
| 2014-12-11 | Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus | Linus Torvalds |
| 2014-11-24 | MIPS: Add CP0 macros for extended EntryLo registers | Steven J. Hill |
| 2014-11-24 | MIPS: define bits introduced for hybrid FPRs | Paul Burton |
| 2014-11-24 | MIPS: cpu-probe: Set the FTLB probability bit on supported cores | Markos Chandras |
| 2014-11-07 | MIPS: Fix build with binutils 2.24.51+ | Manuel Lauss |
| 2014-08-02 | MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFT | Dan Carpenter |
| 2014-08-02 | MIPS: define MAAR register accessors & bits | Paul Burton |
| 2014-08-02 | MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions | Leonid Yegoshin |
| 2014-08-02 | MIPS: asm: Add register definitions for Hardware Table Walker | Markos Chandras |
| 2014-05-30 | MIPS: Add function get_ebase_cpunum | David Daney |
| 2014-05-24 | MIPS: MT: Remove SMTC support | Ralf Baechle |
| 2014-05-23 | MIPS: Disable MIPS16/microMIPS crap for platforms not supporting these ASEs. | Ralf Baechle |
| 2014-03-26 | MIPS: Add MSA register definitions & access | Paul Burton |
| 2014-03-06 | MIPS: Add CP0 CMGCRBase definitions & accessor | Paul Burton |
| 2014-03-06 | MIPS: Define Config1 cache field shifts & sizes | Paul Burton |
| 2014-03-06 | MIPS: mm: c-r4k: Detect instruction cache aliases | Markos Chandras |
| 2014-01-23 | MIPS: include linux/types.h | Qais Yousef |
| 2014-01-22 | MIPS: Add support for FTLBs | Leonid Yegoshin |
| 2014-01-22 | MIPS: Add function for flushing the TLB using the TLBINV instruction | Leonid Yegoshin |
| 2014-01-22 | MIPS: features: Add initial support for Segmentation Control registers | Steven J. Hill |
| 2014-01-22 | MIPS: Add missing bits for Config registers | Leonid Yegoshin |
