summaryrefslogtreecommitdiff
path: root/arch/mips
AgeCommit message (Collapse)Author
2020-12-04MIPS: Enable GCOVXingxing Su
Enable gcov profiling of the entire kernel on mips. Required changes include disabling profiling for: * arch/kernel/boot/compressed: not linked to main kernel. Lightly tested on Loongson 3A3000 an 3A4000, seems to work as expected. without "GCOV_PROFILE := n" in compressed Makefile, build errors as follows: ... ld: arch/mips/boot/compressed/string.o:(.data+0x88): undefined reference to `__gcov_merge_add' ld: arch/mips/boot/compressed/string.o: in function `_GLOBAL__sub_I_00100_0_memcpy': string.c:(.text.startup+0x4): undefined reference to `__gcov_init' ld: arch/mips/boot/compressed/string.o: in function `_GLOBAL__sub_D_00100_1_memcpy': string.c:(.text.exit+0x0): undefined reference to `__gcov_exit' ... Signed-off-by: Youling Tang <tangyouling@loongson.cn> Signed-off-by: Xingxing Su <suxingxing@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-12-04MIPS: configs: drop unused BACKLIGHT_GENERIC optionAndrey Zhizhikin
Commit 7ecdea4a0226 ("backlight: generic_bl: Remove this driver as it is unused") removed geenric_bl driver from the tree, together with corresponding config option. Remove BACKLIGHT_GENERIC config item from all MIPS configurations. Fixes: 7ecdea4a0226 ("backlight: generic_bl: Remove this driver as it is unused") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Sam Ravnborg <sam@ravnborg.org> Cc: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-12-03Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
Conflicts: drivers/net/ethernet/ibm/ibmvnic.c Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-12-01net: Add SO_BUSY_POLL_BUDGET socket optionBjörn Töpel
This option lets a user set a per socket NAPI budget for busy-polling. If the options is not set, it will use the default of 8. Signed-off-by: Björn Töpel <bjorn.topel@intel.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Reviewed-by: Jakub Kicinski <kuba@kernel.org> Link: https://lore.kernel.org/bpf/20201130185205.196029-3-bjorn.topel@gmail.com
2020-12-01net: Introduce preferred busy-pollingBjörn Töpel
The existing busy-polling mode, enabled by the SO_BUSY_POLL socket option or system-wide using the /proc/sys/net/core/busy_read knob, is an opportunistic. That means that if the NAPI context is not scheduled, it will poll it. If, after busy-polling, the budget is exceeded the busy-polling logic will schedule the NAPI onto the regular softirq handling. One implication of the behavior above is that a busy/heavy loaded NAPI context will never enter/allow for busy-polling. Some applications prefer that most NAPI processing would be done by busy-polling. This series adds a new socket option, SO_PREFER_BUSY_POLL, that works in concert with the napi_defer_hard_irqs and gro_flush_timeout knobs. The napi_defer_hard_irqs and gro_flush_timeout knobs were introduced in commit 6f8b12d661d0 ("net: napi: add hard irqs deferral feature"), and allows for a user to defer interrupts to be enabled and instead schedule the NAPI context from a watchdog timer. When a user enables the SO_PREFER_BUSY_POLL, again with the other knobs enabled, and the NAPI context is being processed by a softirq, the softirq NAPI processing will exit early to allow the busy-polling to be performed. If the application stops performing busy-polling via a system call, the watchdog timer defined by gro_flush_timeout will timeout, and regular softirq handling will resume. In summary; Heavy traffic applications that prefer busy-polling over softirq processing should use this option. Example usage: $ echo 2 | sudo tee /sys/class/net/ens785f1/napi_defer_hard_irqs $ echo 200000 | sudo tee /sys/class/net/ens785f1/gro_flush_timeout Note that the timeout should be larger than the userspace processing window, otherwise the watchdog will timeout and fall back to regular softirq processing. Enable the SO_BUSY_POLL/SO_PREFER_BUSY_POLL options on your socket. Signed-off-by: Björn Töpel <bjorn.topel@intel.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Reviewed-by: Jakub Kicinski <kuba@kernel.org> Link: https://lore.kernel.org/bpf/20201130185205.196029-2-bjorn.topel@gmail.com
2020-11-29Merge tag 'locking-urgent-2020-11-29' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull locking fixes from Thomas Gleixner: "Two more places which invoke tracing from RCU disabled regions in the idle path. Similar to the entry path the low level idle functions have to be non-instrumentable" * tag 'locking-urgent-2020-11-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: intel_idle: Fix intel_idle() vs tracing sched/idle: Fix arch_cpu_idle() vs tracing
2020-11-27Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
Trivial conflict in CAN, keep the net-next + the byteswap wrapper. Conflicts: drivers/net/can/usb/gs_usb.c Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-27Merge tag 'asm-generic-fixes-5.10-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic Pull asm-generic fix from Arnd Bergmann: "Add correct MAX_POSSIBLE_PHYSMEM_BITS setting to asm-generic. This is a single bugfix for a bug that Stefan Agner found on 32-bit Arm, but that exists on several other architectures" * tag 'asm-generic-fixes-5.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: arch: pgtable: define MAX_POSSIBLE_PHYSMEM_BITS where needed
2020-11-27Merge branch 'linus' into sched/core, to resolve semantic conflictIngo Molnar
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2020-11-27MIPS: Loongson64: Fix up reserving kernel memory rangeJinyang He
Reserve memory from &_text to &_end. Otherwise if kernel address was modified, the memory range of start_pfn to kernel_start_pfn would be reserved. Then we could not use this range. Signed-off-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-27MIPS: mm: Remove unused is_aligned_hugepage_rangeThomas Bogendoerfer
Function is_aligned_hugepage_range is no longer needed. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-27MIPS: No need to check CPU 0 in {loongson3,bmips,octeon}_cpu_disable()Tiezhu Yang
After commit 9cce844abf07 ("MIPS: CPU#0 is not hotpluggable"), c->hotpluggable is 0 for CPU 0 and it will not generate a control file in sysfs for this CPU: [root@linux loongson]# cat /sys/devices/system/cpu/cpu0/online cat: /sys/devices/system/cpu/cpu0/online: No such file or directory [root@linux loongson]# echo 0 > /sys/devices/system/cpu/cpu0/online bash: /sys/devices/system/cpu/cpu0/online: Permission denied So no need to check CPU 0 in {loongson3,bmips,octeon}_cpu_disable(), just remove them. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-27MIPS: Loongson64: Add KASLR supportJinyang He
Provide a weak plat_get_fdt() in relocate.c in case some platform enable USE_OF while plat_get_fdt() is useless. 1MB RELOCATION_TABLE_SIZE is small for Loongson64 because too many instructions should be relocated. 2MB is enough in present. Add KASLR support for Loongson64. KASLR(kernel address space layout randomization) To enable KASLR on Loongson64: First, make loongson3_defconfig. Then, enable CONFIG_RELOCATABLE and CONFIG_RANDOMIZE_BASE. Finally, compile the kernel. To test KASLR on Loongson64: Start machine with KASLR kernel. The first time: # cat /proc/iomem 00200000-0effffff : System RAM 02f30000-03895e9f : Kernel code 03895ea0-03bc7fff : Kernel data 03e30000-04f43f7f : Kernel bss The second time: # cat /proc/iomem 00200000-0effffff : System RAM 022f0000-02c55e9f : Kernel code 02c55ea0-02f87fff : Kernel data 031f0000-04303f7f : Kernel bss We see that code, data and bss sections become randomize. Signed-off-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-27MIPS: KASLR: Correct valid bits in apply_r_mips_26_rel()Jinyang He
Apply_r_mips_26_rel() relocates instructions like j, jal and etc. These instructions consist of 6bits function field and 26bits address field. The value of target_addr as follows, ================================================================= | high 4bits | low 28bits | ================================================================= |the high 4bits of this PC | the low 26bits of instructions << 2| ================================================================= Thus, loc_orig and log_new both need high 4bits rather than high 6bits. Signed-off-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-27crypto: mips/octeon - Fix sparse endianness warningsHerbert Xu
This patch fixes a number of endianness warnings in the mips/octeon code. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-11-24smp: Cleanup smp_call_function*()Peter Zijlstra
Get rid of the __call_single_node union and cleanup the API a little to avoid external code relying on the structure layout as much. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Frederic Weisbecker <frederic@kernel.org>
2020-11-24sched/idle: Fix arch_cpu_idle() vs tracingPeter Zijlstra
We call arch_cpu_idle() with RCU disabled, but then use local_irq_{en,dis}able(), which invokes tracing, which relies on RCU. Switch all arch_cpu_idle() implementations to use raw_local_irq_{en,dis}able() and carefully manage the lockdep,rcu,tracing state like we do in entry. (XXX: we really should change arch_cpu_idle() to not return with interrupts enabled) Reported-by: Sven Schnelle <svens@linux.ibm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Mark Rutland <mark.rutland@arm.com> Link: https://lkml.kernel.org/r/20201120114925.594122626@infradead.org
2020-11-23arch: move SA_* definitions to generic headersPeter Collingbourne
Most architectures with the exception of alpha, mips, parisc and sparc use the same values for these flags. Move their definitions into asm-generic/signal-defs.h and allow the architectures with non-standard values to override them. Also, document the non-standard flag values in order to make it easier to add new generic flags in the future. A consequence of this change is that on powerpc and x86, the constants' values aside from SA_RESETHAND change signedness from unsigned to signed. This is not expected to impact realistic use of these constants. In particular the typical use of the constants where they are or'ed together and assigned to sa_flags (or another int variable) would not be affected. Signed-off-by: Peter Collingbourne <pcc@google.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: "Eric W. Biederman" <ebiederm@xmission.com> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Link: https://linux-review.googlesource.com/id/Ia3849f18b8009bf41faca374e701cdca36974528 Link: https://lkml.kernel.org/r/b6d0d1ec34f9ee93e1105f14f288fba5f89d1f24.1605235762.git.pcc@google.com Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
2020-11-23Merge 5.10-rc5 into staging-testingGreg Kroah-Hartman
We want the staging/IIO fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-11-20crypto: sha - split sha.h into sha1.h and sha2.hEric Biggers
Currently <crypto/sha.h> contains declarations for both SHA-1 and SHA-2, and <crypto/sha3.h> contains declarations for SHA-3. This organization is inconsistent, but more importantly SHA-1 is no longer considered to be cryptographically secure. So to the extent possible, SHA-1 shouldn't be grouped together with any of the other SHA versions, and usage of it should be phased out. Therefore, split <crypto/sha.h> into two headers <crypto/sha1.h> and <crypto/sha2.h>, and make everyone explicitly specify whether they want the declarations for SHA-1, SHA-2, or both. This avoids making the SHA-1 declarations visible to files that don't want anything to do with SHA-1. It also prepares for potentially moving sha1.h into a new insecure/ or dangerous/ directory. Signed-off-by: Eric Biggers <ebiggers@google.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-11-19Merge https://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-19MIPS: Loongson64: Fix wrong scache size when execute lscpuTiezhu Yang
As the user manual and code comment said, Loongson-3 has 4-scache banks, while Loongson-2K has only 2 banks, so we should multiply the number of scache banks, this multiply operation should be done by c->scache.sets instead of scache_size, otherwise we will get the wrong scache size when execute lscpu. For example, the scache size should be 8192K instead of 2048K on the Loongson 3A3000 and 3A4000 platform, we can see the related info in the following boot message: [loongson@linux ~]$ dmesg | grep "Unified secondary cache" [ 0.000000] Unified secondary cache 8192kB 16-way, linesize 64 bytes. [ 4.061909] Unified secondary cache 8192kB 16-way, linesize 64 bytes. [ 4.125629] Unified secondary cache 8192kB 16-way, linesize 64 bytes. [ 4.188379] Unified secondary cache 8192kB 16-way, linesize 64 bytes. E.g. without this patch: [loongson@linux ~]$ cat /sys/devices/system/cpu/cpu*/cache/index2/size 2048K 2048K 2048K 2048K [loongson@linux ~]$ lscpu | grep "L2 cache" L2 cache: 2048K With this patch: [loongson@linux ~]$ cat /sys/devices/system/cpu/cpu*/cache/index2/size 8192K 8192K 8192K 8192K [loongson@linux ~]$ lscpu | grep "L2 cache" L2 cache: 8192K Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-19MIPS: Remove cpu_has_6k_cache and cpu_has_8k_cache in cpu_cache_init()Tiezhu Yang
Since commit 02cf2119684e ("Cleanup the mess in cpu_cache_init."), cpu_has_6k_cache and cpu_has_8k_cache have no user, r6k_cache_init() and r8k_cache_init() are not defined for over 15 years, just remove them. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-19MIPS: mm: Clean up setup of protection mapThomas Bogendoerfer
Protection map difference between RIXI and non RIXI cpus is _PAGE_NO_EXEC and _PAGE_NO_READ usage. Both already take care of cpu_has_rixi while setting up the page bits. So we just need one setup of protection map and can drop the now unused (and broken for RIXI) PAGE_* defines. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-19MIPS: mm: shorten lines by using macroThomas Bogendoerfer
Introduce helper macro to make lines shorter. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-19MIPS: kvm: Use vm_get_page_prot to get protection bitsThomas Bogendoerfer
MIPS protection bits are setup during runtime so using defines like PAGE_SHARED ignores this runtime changes. Using vm_get_page_prot to get correct page protection fixes this. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-19MIPS: vdso: Use vma page protection for remappingThomas Bogendoerfer
MIPS protection bits are setup during runtime so using defines like PAGE_READONLY ignores these runtime changes. To fix this we simply use the page protection of the setup vma. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-17net: wan: Delete the DLCI / SDLA driversXie He
The DLCI driver (dlci.c) implements the Frame Relay protocol. However, we already have another newer and better implementation of Frame Relay provided by the HDLC_FR driver (hdlc_fr.c). The DLCI driver's implementation of Frame Relay is used by only one hardware driver in the kernel - the SDLA driver (sdla.c). The SDLA driver provides Frame Relay support for the Sangoma S50x devices. However, the vendor provides their own driver (along with their own multi-WAN-protocol implementations including Frame Relay), called WANPIPE. I believe most users of the hardware would use the vendor-provided WANPIPE driver instead. (The WANPIPE driver was even once in the kernel, but was deleted in commit 8db60bcf3021 ("[WAN]: Remove broken and unmaintained Sangoma drivers.") because the vendor no longer updated the in-kernel WANPIPE driver.) Cc: Mike McLagan <mike.mclagan@linux.org> Signed-off-by: Xie He <xie.he.0141@gmail.com> Link: https://lore.kernel.org/r/20201114150921.685594-1-xie.he.0141@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-17mips: bmips: dts: add BCM63268 reset controller supportÁlvaro Fernández Rojas
BCM63268 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-17mips: bmips: dts: add BCM6368 reset controller supportÁlvaro Fernández Rojas
BCM6368 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-17mips: bmips: dts: add BCM6362 reset controller supportÁlvaro Fernández Rojas
BCM6362 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-17mips: bmips: dts: add BCM6358 reset controller supportÁlvaro Fernández Rojas
BCM6358 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-17mips: bmips: dts: add BCM6328 reset controller supportÁlvaro Fernández Rojas
BCM6328 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-17mips: bmips: select ARCH_HAS_RESET_CONTROLLERÁlvaro Fernández Rojas
This allows to add reset controllers support. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-17MIPS: Ingenic: Refresh defconfig for Ingenic SoCs based boards.周琰杰 (Zhou Yanjie)
1.Refresh defconfig of CI20 to support OTG and RNG. 2.Refresh defconfig of CU1000-Neo to support OTG/RNG/OST/SC16IS752. 3.Refresh defconfig of CU1830-Neo to support OTG/DTRNG/OST/SC16IS752. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Tested by: H. Nikolaus Schaller <hns@goldelico.com> # CI20/jz4780 Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-17MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.周琰杰 (Zhou Yanjie)
1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20. 2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752 nodes for CU1000-Neo. 3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752 nodes for CU1830-Neo. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Tested by: H. Nikolaus Schaller <hns@goldelico.com> # CI20/jz4780 Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-17Merge tag 'mips_fixes_5.10_1' into mips-nextThomas Bogendoerfer
Pull in mips-fixes to get memblock fix. - fix bug preventing booting on several platforms - fix for build error, when modules need has_transparent_hugepage - fix for memleak in alchemy clk setup Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-17MIPS: Alchemy: Fix memleak in alchemy_clk_setup_cpuZhang Qilong
If the clk_register fails, we should free h before function returns to prevent memleak. Fixes: 474402291a0ad ("MIPS: Alchemy: clock framework integration of onchip clocks") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-17MIPS: kernel: Fix for_each_memblock conversionThomas Bogendoerfer
The loop over all memblocks works with PFNs and not physical addresses, so we need for_each_mem_pfn_range(). Fixes: b10d6bca8720 ("arch, drivers: replace for_each_membock() with for_each_mem_range()") Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Reviewed-by: Mike Rapoport <rppt@linux.ibm.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
2020-11-16arch: pgtable: define MAX_POSSIBLE_PHYSMEM_BITS where neededArnd Bergmann
Stefan Agner reported a bug when using zsram on 32-bit Arm machines with RAM above the 4GB address boundary: Unable to handle kernel NULL pointer dereference at virtual address 00000000 pgd = a27bd01c [00000000] *pgd=236a0003, *pmd=1ffa64003 Internal error: Oops: 207 [#1] SMP ARM Modules linked in: mdio_bcm_unimac(+) brcmfmac cfg80211 brcmutil raspberrypi_hwmon hci_uart crc32_arm_ce bcm2711_thermal phy_generic genet CPU: 0 PID: 123 Comm: mkfs.ext4 Not tainted 5.9.6 #1 Hardware name: BCM2711 PC is at zs_map_object+0x94/0x338 LR is at zram_bvec_rw.constprop.0+0x330/0xa64 pc : [<c0602b38>] lr : [<c0bda6a0>] psr: 60000013 sp : e376bbe0 ip : 00000000 fp : c1e2921c r10: 00000002 r9 : c1dda730 r8 : 00000000 r7 : e8ff7a00 r6 : 00000000 r5 : 02f9ffa0 r4 : e3710000 r3 : 000fdffe r2 : c1e0ce80 r1 : ebf979a0 r0 : 00000000 Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user Control: 30c5383d Table: 235c2a80 DAC: fffffffd Process mkfs.ext4 (pid: 123, stack limit = 0x495a22e6) Stack: (0xe376bbe0 to 0xe376c000) As it turns out, zsram needs to know the maximum memory size, which is defined in MAX_PHYSMEM_BITS when CONFIG_SPARSEMEM is set, or in MAX_POSSIBLE_PHYSMEM_BITS on the x86 architecture. The same problem will be hit on all 32-bit architectures that have a physical address space larger than 4GB and happen to not enable sparsemem and include asm/sparsemem.h from asm/pgtable.h. After the initial discussion, I suggested just always defining MAX_POSSIBLE_PHYSMEM_BITS whenever CONFIG_PHYS_ADDR_T_64BIT is set, or provoking a build error otherwise. This addresses all configurations that can currently have this runtime bug, but leaves all other configurations unchanged. I looked up the possible number of bits in source code and datasheets, here is what I found: - on ARC, CONFIG_ARC_HAS_PAE40 controls whether 32 or 40 bits are used - on ARM, CONFIG_LPAE enables 40 bit addressing, without it we never support more than 32 bits, even though supersections in theory allow up to 40 bits as well. - on MIPS, some MIPS32r1 or later chips support 36 bits, and MIPS32r5 XPA supports up to 60 bits in theory, but 40 bits are more than anyone will ever ship - On PowerPC, there are three different implementations of 36 bit addressing, but 32-bit is used without CONFIG_PTE_64BIT - On RISC-V, the normal page table format can support 34 bit addressing. There is no highmem support on RISC-V, so anything above 2GB is unused, but it might be useful to eventually support CONFIG_ZRAM for high pages. Fixes: 61989a80fb3a ("staging: zsmalloc: zsmalloc memory allocation library") Fixes: 02390b87a945 ("mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS") Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Reviewed-by: Stefan Agner <stefan@agner.ch> Tested-by: Stefan Agner <stefan@agner.ch> Acked-by: Mike Rapoport <rppt@linux.ibm.com> Link: https://lore.kernel.org/linux-mm/bdfa44bf1c570b05d6c70898e2bbb0acf234ecdf.1604762181.git.stefan@agner.ch/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-11-13drivers: staging: retire drivers/staging/goldfishRoman Kiryanov
Android Studio Emulator (goldfish) migrated to Intel HDA. Signed-off-by: Roman Kiryanov <rkir@google.com> Link: https://lore.kernel.org/r/20201112234907.3761694-1-rkir@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-11-12mips: boot: add support for self-extracting FIT images (vmlinuz.itb)Alexander Lobakin
Commit c3e2ee657418 ("MIPS: generic: Add support for zboot") added support for self-extracting images to Generic MIPS. However, the intended way to boot Generic MIPS kernels is using FIT Images and UHI boot protocol, but currently there's no way to make self-extracting FIT Image (only legacy uzImages). Add a target for this named "vmlinuz.itb", which will consist of vmlinuz.bin and selected DT blobs. It will allow to have the advantages of both UHI and self-extracting images. Signed-off-by: Alexander Lobakin <alobakin@pm.me> Acked-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-12mips: boot: clean up self-extracting targets scenariosAlexander Lobakin
1. All final targets like vmlinuz.{bin,ecoff,srec} etc. should reside in $(objtree)/arch/mips/boot, not in the root $(objtree) directory. The only file that should be left there is vmlinuz, similar to other architectures. 2. Add all the targets to $(targets) variable, so they'll be properly accounted by Kbuild. This also allows to remove redundant $(clean-files) (which were missing uzImage BTW). 3. Prefix all targets with $(obj)/$(objtree), depending on their locations. Misc: fix the identation of the 'STRIP' quiet message. Signed-off-by: Alexander Lobakin <alobakin@pm.me> Acked-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-12MIPS: mscc: Add serval supportGregory CLEMENT
Add a device trees and FIT image support for the Microsemi Serval SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-12MIPS: mscc: Add jaguar2 supportGregory CLEMENT
Add a device trees and FIT image support for the Microsemi Jaguar2 SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-12MIPS: mscc: build FIT image for LutonGregory CLEMENT
Luton now has already an u-boot port so let's build FIT images. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-12MIPS: mscc: Add luton PC0B91 device treeGregory CLEMENT
Add a device tree for the Microsemi Luton PCB091 evaluation board. It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-12MIPS: mscc: Add luton dtsiGregory CLEMENT
Add a device tree include file for the Microsemi Luton SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-12MIPS: mscc: Fix configuration name for ocelot legacy boardsGregory CLEMENT
Ocelots is supported by the generic MIPS build so make it clears that LEGACY_BOARD_OCELOT is only needed for legacy boards which didn't have bootloader supporting device tree. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-12MIPS: mscc: Prepare configuration to handle more SoCsGregory CLEMENT
Ocelot belongs to a family of SoC named the VCore III. In order to add these new Soc, use the new symbol SOC_VCOREIII instead of a one dedicated to Ocelot. In order to avoid regression on driver building, the MSCC_OCELOT configuration symbol is kept until the driver will be converted. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
generated by cgit (git 2.34.1) at 2025-04-15 13:19:53 +0000