| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-05-12 | sched/core: Initialize the idle task with preemption disabled | Valentin Schneider |
| 2021-02-09 | openrisc: Use devicetree to determine present cpus | Jan Henrik Weinstock |
| 2020-08-04 | openrisc: Implement proper SMP tlb flushing | Stafford Horne |
| 2020-01-31 | openrisc: use mmgrab | Julia Lawall |
| 2017-11-03 | openrisc: fix possible deadlock scenario during timer sync | Stafford Horne |
| 2017-11-03 | openrisc: add tick timer multi-core sync logic | Stafford Horne |
| 2017-11-03 | openrisc: add cacheflush support to fix icache aliasing | Jan Henrik Weinstock |
| 2017-11-03 | openrisc: sleep instead of spin on secondary wait | Stafford Horne |
| 2017-11-03 | openrisc: fix initial preempt state for secondary cpu tasks | Stafford Horne |
| 2017-11-03 | openrisc: initial SMP support | Stefan Kristiansson |
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index : linux-arm.git | |
| Russell King's ARM Linux kernel tree | Russell King |
| summaryrefslogtreecommitdiff |