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According to the T2080RDB schematics, for the CS4315 PHY, the XFI 1 lane is
connected to SFP 2 and the XFI 2 lane is connected to SFP 1. Change the
device tree to reflect the correct PHY order and port association.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Scott Wood <oss@buserror.net>
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The Cortina PHY is not compatible with IEEE 802.3 clause 45.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
[scottwood: made commit message about compatibility, not driver choice]
Signed-off-by: Scott Wood <oss@buserror.net>
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Describe the PHY topology for all configurations supported by each board
Based on prior work by Andy Fleming <afleming@freescale.com>
Signed-off-by: Shruti Kanetkar <Shruti@freescale.com>
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
Signed-off-by: Scott Wood <oss@buserror.net>
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It makes no sense that some Freescale device tree files are in fsl
directory while some others not. This patch move Freescale device tree
files into fsl folder. To do that the following two steps are made:
- Move Freescale device tree files into fsl folder.
- Update the include path in these files from "fsl/*.dtsi" to "*.dtsi".
Please add "fsl/" prefix when you make dtb using Makefile.
Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
[scottwood: fixed cuImage rule]
Signed-off-by: Scott Wood <scottwood@freescale.com>
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