linux-arm.git - Russell King's ARM Linux kernel tree

Age	Commit message (Expand)	Author
2023-07-03	Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm	Linus Torvalds
2023-06-08	riscv: Add new csr defines related to vector extension	Greentime Hu
2023-06-06	RISC-V: KVM: Redirect AMO load/store misaligned traps to guest	wchen
2023-05-05	Merge tag 'kvm-riscv-6.4-1' of https://github.com/kvm-riscv/linux into HEAD	Paolo Bonzini
2023-04-21	RISC-V: KVM: Drop the _MASK suffix from hgatp.VMID mask defines	Anup Patel
2023-04-21	RISC-V: Add AIA related CSR defines	Anup Patel
2023-03-23	riscv: entry: Convert to generic entry	Guo Ren
2022-08-11	RISC-V: Add Sstc extension support	Palmer Dabbelt
2022-08-11	RISC-V: Add SSTC extension CSR details	Atish Patra
2022-07-29	RISC-V: KVM: Add support for Svpbmt inside Guest/VM	Anup Patel
2022-05-31	Merge tag 'riscv-for-linus-5.19-mw0' of git://git.kernel.org/pub/scm/linux/ke...	Linus Torvalds
2022-05-20	RISC-V: KVM: Add Sv57x4 mode support for G-stage	Anup Patel
2022-04-26	riscv: compat: syscall: Add entry.S implementation	Guo Ren
2022-03-21	perf: RISC-V: Add support for SBI PMU and Sscofpmf	Palmer Dabbelt
2022-03-21	RISC-V: Add sscofpmf extension support	Atish Patra
2022-03-21	RISC-V: Add CSR encodings for all HPMCOUNTERS	Atish Patra
2022-02-14	riscv: mm: Set sv57 on defaultly	Qinglin Pan
2022-01-19	riscv: Implement sv48 support	Alexandre Ghiti
2021-10-04	RISC-V: Add hypervisor extension related CSR defines	Anup Patel
2021-04-26	riscv: Introduce alternative mechanism to apply errata solution	Vincent Chen
2021-02-18	RISC-V: Implement ASID allocator	Anup Patel
2020-05-04	RISC-V: Remove N-extension related defines	Anup Patel
2020-02-18	riscv: set pmp configuration if kernel is running in M-mode	Greentime Hu
2020-01-04	riscv: prefix IRQ_ macro names with an RV_ namespace	Paul Walmsley
2019-11-17	riscv: clear the instruction cache and all registers when booting	Christoph Hellwig
2019-11-17	riscv: read the hart ID from mhartid on boot	Damien Le Moal
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner
2019-05-16	RISC-V: Access CSRs using CSR numbers	Anup Patel
2019-05-16	RISC-V: Add interrupt related SCAUSE defines in asm/csr.h	Anup Patel
2019-05-16	RISC-V: Use tabs to align macro values in asm/csr.h	Anup Patel
2018-08-13	RISC-V: add a definition for the SIE SEIE bit	Christoph Hellwig
2018-01-30	riscv: rename sptbr to satp	Christoph Hellwig
2018-01-07	riscv: rename SR_* constants to match the spec	Christoph Hellwig
2017-09-26	RISC-V: Generic library routines and assembly	Palmer Dabbelt