| Age | Commit message (Expand) | Author |
|---|
| 2021-04-26 | riscv: Introduce alternative mechanism to apply errata solution | Vincent Chen |
| 2021-02-18 | RISC-V: Implement ASID allocator | Anup Patel |
| 2020-05-04 | RISC-V: Remove N-extension related defines | Anup Patel |
| 2020-02-18 | riscv: set pmp configuration if kernel is running in M-mode | Greentime Hu |
| 2020-01-04 | riscv: prefix IRQ_ macro names with an RV_ namespace | Paul Walmsley |
| 2019-11-17 | riscv: clear the instruction cache and all registers when booting | Christoph Hellwig |
| 2019-11-17 | riscv: read the hart ID from mhartid on boot | Damien Le Moal |
| 2019-11-05 | riscv: abstract out CSR names for supervisor vs machine mode | Christoph Hellwig |
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner |
| 2019-05-16 | RISC-V: Access CSRs using CSR numbers | Anup Patel |
| 2019-05-16 | RISC-V: Add interrupt related SCAUSE defines in asm/csr.h | Anup Patel |
| 2019-05-16 | RISC-V: Use tabs to align macro values in asm/csr.h | Anup Patel |
| 2018-08-13 | RISC-V: add a definition for the SIE SEIE bit | Christoph Hellwig |
| 2018-01-30 | riscv: rename sptbr to satp | Christoph Hellwig |
| 2018-01-07 | riscv: rename SR_* constants to match the spec | Christoph Hellwig |
| 2017-09-26 | RISC-V: Generic library routines and assembly | Palmer Dabbelt |
