| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-05-16 | RISC-V: Access CSRs using CSR numbers | Anup Patel |
| 2019-05-16 | RISC-V: Add interrupt related SCAUSE defines in asm/csr.h | Anup Patel |
| 2019-05-16 | RISC-V: Use tabs to align macro values in asm/csr.h | Anup Patel |
| 2018-08-13 | RISC-V: add a definition for the SIE SEIE bit | Christoph Hellwig |
| 2018-01-30 | riscv: rename sptbr to satp | Christoph Hellwig |
| 2018-01-07 | riscv: rename SR_* constants to match the spec | Christoph Hellwig |
| 2017-09-26 | RISC-V: Generic library routines and assembly | Palmer Dabbelt |
 |
index : linux-arm.git | |
| Russell King's ARM Linux kernel tree | Russell King |
| summaryrefslogtreecommitdiff |