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path: root/arch/riscv/include/asm/sbi.h
AgeCommit message (Expand)Author
2020-03-31RISC-V: Add SBI HSM extension definitionsAtish Patra
2020-03-31RISC-V: Export SBI error to linux error mapping functionAtish Patra
2020-03-31RISC-V: Implement new SBI v0.2 extensionsAtish Patra
2020-03-31RISC-V: Introduce a new config for SBI v0.1Atish Patra
2020-03-31RISC-V: Add SBI v0.2 extension definitionsAtish Patra
2020-03-31RISC-V: Add basic support for SBI v0.2Atish Patra
2020-03-31RISC-V: Mark existing SBI as 0.1 SBI.Atish Patra
2019-11-17riscv: provide native clint access for M-modeChristoph Hellwig
2019-11-13riscv: add support for MMIO access to the timer registersChristoph Hellwig
2019-11-13riscv: implement remote sfence.i using IPIsChristoph Hellwig
2019-11-13riscv: poison SBI calls for M-modeChristoph Hellwig
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner
2019-05-16riscv: fix sbi_remote_sfence_vma{,_asid}.Gary Guo
2017-09-26RISC-V: Device, timer, IRQs, and the SBIPalmer Dabbelt