| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-09-05 | riscv: move the TLB flush logic out of line | Christoph Hellwig |
| 2019-09-05 | riscv: cleanup riscv_cpuid_to_hartid_mask | Christoph Hellwig |
| 2019-08-13 | riscv: fix flush_tlb_range() end address for flush_tlb_page() | Paul Walmsley |
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner |
| 2018-10-22 | RISC-V: Use Linux logical CPU number instead of hartid | Atish Patra |
| 2018-06-07 | riscv: use NULL instead of a plain 0 | Luc Van Oostenryck |
| 2018-01-30 | RISC-V: Limit the scope of TLB shootdowns | Andrew Waterman |
| 2018-01-07 | riscv: remove CONFIG_MMU ifdefs | Christoph Hellwig |
| 2017-12-01 | RISC-V: User-Visible Changes | Palmer Dabbelt |
| 2017-11-30 | RISC-V: Flush I$ when making a dirty page executable | Andrew Waterman |
| 2017-11-28 | RISC-V: `sfence.vma` orderes the instruction cache | Palmer Dabbelt |
| 2017-09-26 | RISC-V: Atomic and Locking Code | Palmer Dabbelt |
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index : linux-arm.git | |
| Russell King's ARM Linux kernel tree | Russell King |
| summaryrefslogtreecommitdiff |