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path: root/arch/riscv/kernel/cpu.c
AgeCommit message (Expand)Author
2023-05-05Merge tag 'kvm-riscv-6.4-1' of https://github.com/kvm-riscv/linux into HEADPaolo Bonzini
2023-04-21RISC-V: Detect AIA CSRs from ISA stringAnup Patel
2023-04-18Merge patch series "RISC-V Hardware Probing User Interface"Palmer Dabbelt
2023-04-18RISC-V: Move struct riscv_cpuinfo to new headerEvan Green
2023-03-15Merge patch series "RISC-V: Apply Zicboz to clear_page"Palmer Dabbelt
2023-03-14RISC-V: Add Zicboz detection and block size parsingAndrew Jones
2023-03-09Merge patch series "riscv, mm: detect svnapot cpu support at runtime"Palmer Dabbelt
2023-03-07riscv: mm: modify pte format for SvnapotQinglin Pan
2023-02-21RISC-V: fix ordering of Zbb extensionHeiko Stuebner
2023-01-31RISC-V: add zbb support to string functionsHeiko Stuebner
2023-01-19Merge patch series "Putting some basic order on isa extension lists"Palmer Dabbelt
2023-01-17RISC-V: resort all extensions in consistent ordersConor Dooley
2023-01-17RISC-V: clarify ISA string ordering rules in cpu.cConor Dooley
2022-12-14Merge tag 'riscv-for-linus-6.2-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds
2022-10-27RISC-V: Fix /proc/cpuinfo cpumask warningAndrew Jones
2022-10-27RISC-V: Cache SBI vendor valuesHeiko Stuebner
2022-10-14Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds
2022-10-13RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo outputPalmer Dabbelt
2022-10-11Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds
2022-10-06RISC-V: Print SSTC in canonical orderPalmer Dabbelt
2022-10-03RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo outputAnup Patel
2022-10-02RISC-V: Probe Svinval extension form ISA stringMayuresh Chitale
2022-08-11RISC-V: Add Sstc extension supportPalmer Dabbelt
2022-08-11RISC-V: Enable sstc extension parsing from DTAtish Patra
2022-08-11arch/riscv: add Zihintpause supportDao Lu
2022-08-10riscv: implement Zicbom-based CMO instructions + the t-head variantPalmer Dabbelt
2022-07-28riscv: Add support for non-coherent devices using zicbom extensionHeiko Stuebner
2022-07-19riscv: cpu: Add 64bit hartid support on RV64Sunil V L
2022-05-21riscv: Don't output a bogus mmu-type on a no MMU kernelNiklas Cassel
2022-05-11riscv: add RISC-V Svpbmt extension supportHeiko Stuebner
2022-03-31riscv: cpu.c: don't use kernel-doc markers for commentsRandy Dunlap
2022-03-30RISC-V: Fix a comment typo in riscv_of_parent_hartid()Atish Patra
2022-03-21perf: RISC-V: Add support for SBI PMU and SscofpmfPalmer Dabbelt
2022-03-21RISC-V: Add sscofpmf extension supportAtish Patra
2022-03-17RISC-V: Provide a fraemework for RISC-V ISA extensionsPalmer Dabbelt
2022-03-17RISC-V: Improve /proc/cpuinfo output for ISA extensionsAtish Patra
2022-02-14riscv: mm: Set sv57 on defaultlyQinglin Pan
2022-01-19riscv: Use pgtable_l4_enabled to output mmu_type in cpuinfoAlexandre Ghiti
2021-10-20riscv: Use of_get_cpu_hwid()Rob Herring
2020-06-09RISC-V: Rename and move plic_find_hart_id() to arch directoryAnup Patel
2019-10-28RISC-V: Remove unsupported isa string info printAtish Patra
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner
2019-04-30RISC-V: Add RISC-V specific arch_match_cpu_phys_idAtish Patra
2019-03-04RISC-V: Remove NR_CPUs check during hartid search from DTAtish Patra
2019-02-11riscv: treat cpu devicetree nodes without status as enabledJohan Hovold
2019-02-11riscv: fix riscv_of_processor_hartid() commentJohan Hovold
2019-02-11riscv: add missing newlines to printk messagesJohan Hovold
2018-12-21RISC-V: Fix of_node_* refcountAtish Patra
2018-11-20RISC-V: recognize S/U mode bits in print_isaPatrick Stählin
2018-10-22RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfoAnup Patel