| Age | Commit message (Expand) | Author |
|---|
| 2023-06-20 | riscv: replace deprecated scall with ecall | Fangrui Song |
| 2023-06-08 | riscv: Disable Vector Instructions for kernel itself | Guo Ren |
| 2023-03-23 | riscv: entry: Consolidate general regs saving/restoring | Jisheng Zhang |
| 2023-03-23 | riscv: entry: Consolidate ret_from_kernel_thread into ret_from_fork | Jisheng Zhang |
| 2023-03-23 | riscv: entry: Convert to generic entry | Guo Ren |
| 2022-12-12 | Merge patch series "RISC-V: Align the shadow stack" | Palmer Dabbelt |
| 2022-12-08 | Merge patch "RISC-V: Fix unannoted hardirqs-on in return to userspace slow-path" | Palmer Dabbelt |
| 2022-12-08 | RISC-V: Fix unannoted hardirqs-on in return to userspace slow-path | Andrew Bresticker |
| 2022-12-05 | riscv: stacktrace: Make walk_stackframe cross pt_regs frame | Guo Ren |
| 2022-11-29 | riscv: fix race when vmap stack overflow | Jisheng Zhang |
| 2022-06-29 | context_tracking: Split user tracking Kconfig | Frederic Weisbecker |
| 2022-06-29 | context_tracking: Rename context_tracking_user_enter/exit() to user_enter/exi... | Frederic Weisbecker |
| 2022-04-26 | riscv: compat: syscall: Add entry.S implementation | Guo Ren |
| 2022-03-25 | Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/ke... | Linus Torvalds |
| 2022-03-22 | RISC-V: Add support for restartable sequence | Vincent Chen |
| 2022-02-24 | riscv: fix oops caused by irqsoff latency tracer | Changbin Du |
| 2021-11-01 | Merge tag 'cpu-to-thread_info-v5.16-rc1' of git://git.kernel.org/pub/scm/linu... | Linus Torvalds |
| 2021-10-26 | irq: riscv: perform irqentry in entry code | Mark Rutland |
| 2021-09-30 | riscv: rely on core code to keep thread_info::cpu updated | Ard Biesheuvel |
| 2021-07-06 | riscv: add VMAP_STACK overflow detection | Tong Tiangen |
| 2021-05-06 | Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/ke... | Linus Torvalds |
| 2021-04-26 | riscv: sifive: Apply errata "cip-453" patch | Vincent Chen |
| 2021-04-15 | riscv: keep interrupts disabled for BREAKPOINT exception | Jisheng Zhang |
| 2021-04-01 | riscv,entry: fix misaligned base for excp_vect_table | Zihao Yu |
| 2021-01-12 | riscv: Trace irq on only interrupt is enabled | Atish Patra |
| 2021-01-07 | riscv: Enable interrupts during syscalls with M-Mode | Damien Le Moal |
| 2021-01-07 | riscv: return -ENOSYS for syscall -1 | Andreas Schwab |
| 2020-07-30 | riscv: Cleanup unnecessary define in asm-offset.c | Guo Ren |
| 2020-07-30 | riscv: Enable context tracking | Greentime Hu |
| 2020-07-30 | riscv: Enable LOCKDEP_SUPPORT & fixup TRACE_IRQFLAGS_SUPPORT | Guo Ren |
| 2020-06-09 | RISC-V: Remove do_IRQ() function | Anup Patel |
| 2020-04-09 | Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/... | Linus Torvalds |
| 2020-03-05 | riscv: fix seccomp reject syscall code path | Tycho Andersen |
| 2020-03-03 | RISC-V: Inline the assembly register save/restore macros | Palmer Dabbelt |
| 2020-01-28 | Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/ker... | Linus Torvalds |
| 2019-12-27 | riscv: reject invalid syscalls below -1 | David Abdurachmanov |
| 2019-12-08 | sched/rt, riscv: Use CONFIG_PREEMPTION | Thomas Gleixner |
| 2019-11-22 | Merge branch 'next/nommu' into for-next | Paul Walmsley |
| 2019-11-17 | riscv: add nommu support | Christoph Hellwig |
| 2019-11-05 | riscv: abstract out CSR names for supervisor vs machine mode | Christoph Hellwig |
| 2019-10-29 | riscv: add support for SECCOMP and SECCOMP_FILTER | David Abdurachmanov |
| 2019-10-09 | RISC-V: entry: Remove unneeded need_resched() loop | Valentin Schneider |
| 2019-10-01 | RISC-V: Clear load reservations while restoring hart contexts | Palmer Dabbelt |
| 2019-09-20 | riscv: Avoid interrupts being erroneously enabled in handle_exception() | Vincent Chen |
| 2019-08-30 | riscv: Using CSR numbers to access CSRs | Bin Meng |
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner |
| 2019-05-16 | RISC-V: Access CSRs using CSR numbers | Anup Patel |
| 2019-01-23 | RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=y | Vincent Chen |
| 2019-01-07 | riscv: add audit support | David Abdurachmanov |
| 2018-10-22 | RISC-V: SMP cleanup and new features | Palmer Dabbelt |
