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path: root/arch/riscv/kernel/entry.S
AgeCommit message (Expand)Author
2019-05-16RISC-V: Access CSRs using CSR numbersAnup Patel
2019-01-23RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=yVincent Chen
2019-01-07riscv: add audit supportDavid Abdurachmanov
2018-10-22RISC-V: SMP cleanup and new featuresPalmer Dabbelt
2018-10-22RISC-V: No need to pass scause as arg to do_IRQ()Anup Patel
2018-10-22Extract FPU context operations from entry.SAlan Kao
2018-08-13RISC-V: implement low-level interrupt handlingChristoph Hellwig
2018-03-14RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handlerPalmer Dabbelt
2018-02-20RISC-V: Enable IRQ during exception handlingzongbox@gmail.com
2018-01-30riscv: disable SUM in the exception handlerChristoph Hellwig
2018-01-07riscv: rename SR_* constants to match the specChristoph Hellwig
2017-09-26RISC-V: Task implementationPalmer Dabbelt