summaryrefslogtreecommitdiff
path: root/arch/riscv/kernel/head.S
AgeCommit message (Expand)Author
2023-01-19riscv: fix -Wundef warning for CONFIG_RISCV_BOOT_SPINWAITMasahiro Yamada
2022-06-01riscv: Initialize thread pointer before calling C functionsAlexandre Ghiti
2022-05-25RISC-V: Split out the XIP fixups into their own filePalmer Dabbelt
2022-03-10RISC-V: Add arch functions for non-retentive suspend entry/exitAnup Patel
2022-03-10RISC-V: Rename relocate() and make it globalAnup Patel
2022-01-20RISC-V: Move spinwait booting method to its own configAtish Patra
2022-01-20RISC-V: Move the entire hart selection via lottery to SMPAtish Patra
2022-01-20RISC-V: Use __cpu_up_stack/task_pointer only for spinwait methodAtish Patra
2022-01-20RISC-V: Avoid using per cpu array for ordered bootingAtish Patra
2022-01-19RISC-V: Introduce sv48 support without relocatable kernelPalmer Dabbelt
2022-01-19riscv: Implement sv48 supportAlexandre Ghiti
2022-01-09riscv: head: remove useless __PAGE_ALIGNED_BSS and .balignJisheng Zhang
2022-01-09riscv: head: make secondary_start_common() staticJisheng Zhang
2022-01-07riscv/head: fix misspelling of guaranteedhasheddan
2021-11-13Merge tag 'riscv-for-linus-5.16-mw1' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds
2021-11-01Merge tag 'cpu-to-thread_info-v5.16-rc1' of git://git.kernel.org/pub/scm/linu...Linus Torvalds
2021-10-27riscv: fix misalgned trap vector base addressChen Lu
2021-10-26riscv: remove .text section size limitation for XIPVitaly Wool
2021-09-30riscv: rely on core code to keep thread_info::cpu updatedArd Biesheuvel
2021-07-05riscv: Introduce structure that group all variables regarding kernel mappingAlexandre Ghiti
2021-04-26RISC-V: enable XIPVitaly Wool
2021-04-26riscv: Move kernel mapping outside of linear mappingAlexandre Ghiti
2021-02-18riscv: add BUILTIN_DTB support for MMU-enabled targetsVitaly Wool
2020-12-18Merge tag 'riscv-for-linus-5.11-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds
2020-11-25riscv: Enable ARCH_STACKWALKKefeng Wang
2020-11-05riscv: Set text_offset correctly for M-ModeSean Anderson
2020-10-02RISC-V: Add PE/COFF header for EFI stubAtish Patra
2020-10-02RISC-V: Move DT mapping outof fixmapAnup Patel
2020-09-15RISC-V: Fix duplicate included thread_info.hTian Tao
2020-08-14riscv: Setup exception vector for nommu platformQiu Wenbo
2020-07-30RISC-V: Setup exception vector earlyAtish Patra
2020-05-18RISC-V: Skip setting up PMPs on trapsPalmer Dabbelt
2020-04-03riscv: Add SOC early init supportDamien Le Moal
2020-03-31RISC-V: Add supported for ordered booting method using HSMAtish Patra
2020-03-31RISC-V: Move relocate and few other functions out of __initAtish Patra
2020-02-18riscv: set pmp configuration if kernel is running in M-modeGreentime Hu
2020-01-22riscv: Add KASAN supportNick Hu
2020-01-15riscv: make sure the cores stay looping in .Lsecondary_parkGreentime Hu
2020-01-12riscv: Fixup obvious bug for fp-regs resetGuo Ren
2019-12-20riscv: fix scratch register clearing in M-mode.Greentime Hu
2019-11-17riscv: add nommu supportChristoph Hellwig
2019-11-17riscv: clear the instruction cache and all registers when bootingChristoph Hellwig
2019-11-17riscv: read the hart ID from mhartid on bootDamien Le Moal
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig
2019-09-20arch/riscv: disable excess harts before picking main boot hartXiang Wang
2019-09-16Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds
2019-09-13riscv: modify the Image header to improve compatibility with the ARM64 headerPaul Walmsley
2019-08-30riscv: Using CSR numbers to access CSRsBin Meng
2019-07-11RISC-V: Add an Image header that boot loader can parse.Atish Patra
2019-07-09RISC-V: Setup initial page tables in two stagesAnup Patel