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path: root/arch/riscv/kernel/smp.c
AgeCommit message (Expand)Author
2019-11-17riscv: provide native clint access for M-modeChristoph Hellwig
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig
2019-10-28riscv: add missing header file includesPaul Walmsley
2019-09-20RISC-V: Export kernel symbols for kvmAtish Patra
2019-09-05riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig
2019-09-05riscv: optimize send_ipi_singleChristoph Hellwig
2019-09-05riscv: cleanup send_ipi_maskChristoph Hellwig
2019-09-05riscv: refactor the IPI codeChristoph Hellwig
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner
2019-05-16riscv: move flush_icache_{all,mm} to cacheflush.cGary Guo
2019-05-16RISC-V: Access CSRs using CSR numbersAnup Patel
2019-05-16RISC-V: Fix minor checkpatch issues.Atish Patra
2019-04-30RISC-V: Add RISC-V specific arch_match_cpu_phys_idAtish Patra
2019-03-04RISC-V: Fixmap support and MM cleanupsPalmer Dabbelt
2019-03-04RISC-V: Allow hartid-to-cpuid function to fail.Atish Patra
2019-03-04RISC-V: Move cpuid to hartid mapping to SMP.Atish Patra
2019-01-07riscv: don't stop itself in smp_send_stopAndreas Schwab
2018-10-22RISC-V: Show IPI statsAnup Patel
2018-10-22RISC-V: Use Linux logical CPU number instead of hartidAtish Patra
2018-10-22RISC-V: Add logical CPU indexing for RISC-VAtish Patra
2018-08-13RISC-V: simplify software interrupt / IPI codeChristoph Hellwig
2017-12-01RISC-V: Fixes for clean allmodconfig buildPalmer Dabbelt
2017-11-30RISC-V: Flush I$ when making a dirty page executableAndrew Waterman
2017-11-30RISC-V: Provide stub of setup_profiling_timer()Olof Johansson
2017-09-26RISC-V: Init and Halt CodePalmer Dabbelt