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path: root/arch/riscv/kernel/traps.c
AgeCommit message (Expand)Author
2020-03-16irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offlineAtish Patra
2020-02-18RISC-V: Don't enable all interrupts in trap_init()Anup Patel
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig
2019-10-28riscv: for C functions called only from assembly, mark with __visiblePaul Walmsley
2019-10-28riscv: add missing header file includesPaul Walmsley
2019-10-25riscv: cleanup do_trap_breakChristoph Hellwig
2019-10-14riscv: remove the switch statement in do_trap_break()Vincent Chen
2019-10-07riscv: Correct the handling of unexpected ebreak in do_trap_break()Vincent Chen
2019-10-07riscv: avoid sending a SIGTRAP to a user thread trapped in WARN()Vincent Chen
2019-10-07riscv: avoid kernel hangs when trapped in BUG()Vincent Chen
2019-07-08Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner
2019-05-29signal: Remove the task parameter from force_sig_faultEric W. Biederman
2019-05-29signal: Explicitly call force_sig_fault on currentEric W. Biederman
2019-05-29signal/riscv: Remove tsk parameter from do_trapEric W. Biederman
2019-05-16riscv: Support BUG() in kernel moduleVincent Chen
2019-05-16riscv: Add the support for c.ebreak check in is_valid_bugaddr()Vincent Chen
2019-05-16RISC-V: Access CSRs using CSR numbersAnup Patel
2019-04-25riscv: remove duplicate macros from ptrace.hChristoph Hellwig
2018-08-13RISC-V: Don't increment sepc after breakpoint.Jim Wilson
2018-06-16Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm...Linus Torvalds
2018-06-07riscv: no __user for probe_kernel_address()Luc Van Oostenryck
2018-04-25signal/riscv: Replace do_trap_siginfo with force_sig_faultEric W. Biederman
2018-04-25signal/riscv: Use force_sig_fault where appropriateEric W. Biederman
2018-04-25signal: Ensure every siginfo we send has all bits initializedEric W. Biederman
2017-09-26RISC-V: Init and Halt CodePalmer Dabbelt