| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-07-04 | riscv: ccache: Remove unused variable | Yash Shah | |
| Reading the count register clears the interrupt signal. Currently, the count registers are read into 'regval' variable but the variable is never used. Therefore remove it. V2 of this patch add comments to justify the readl calls without checking the return value. Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> | |||
| 2019-05-16 | RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs | Yash Shah | |
| The driver currently supports only SiFive FU540-C000 platform. The initial version of L2 cache controller driver includes: - Initial configuration reporting at boot up. - Support for ECC related functionality. Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> | |||
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index : linux-arm.git | |
| Russell King's ARM Linux kernel tree | Russell King |
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