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AgeCommit message (Expand)Author
2018-11-01RISC-V: refresh defconfigAnup Patel
2018-10-31Merge tag 'riscv-for-linus-4.20-mw2' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds
2018-10-31lib: Remove umoddi3 and udivmoddi4Palmer Dabbelt
2018-10-31Move EM_RISCV into elf-em.hPalmer Dabbelt
2018-10-31RISC-V: properly determine hardware capsAndreas Schwab
2018-10-31Revert "RISC-V: Select GENERIC_LIB_UMODDI3 on RV32"Palmer Dabbelt
2018-10-31mm: remove include/linux/bootmem.hMike Rapoport
2018-10-31memblock: rename free_all_bootmem to memblock_free_allMike Rapoport
2018-10-31mm: remove CONFIG_HAVE_MEMBLOCKMike Rapoport
2018-10-31mm: remove CONFIG_NO_BOOTMEMMike Rapoport
2018-10-31treewide: remove current_text_addrNick Desaulniers
2018-10-25Merge tag 'riscv-for-linus-4.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds
2018-10-25Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds
2018-10-24Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds
2018-10-22RISC-V: SMP cleanup and new featuresPalmer Dabbelt
2018-10-22RISC-V: Fix some RV32 bugs and build failuresPalmer Dabbelt
2018-10-22riscv: Add support to no-FPU systemsPalmer Dabbelt
2018-10-22RISC-V: Cosmetic menuconfig changesNick Kossifidis
2018-10-22riscv: move GCC version check for ARCH_SUPPORTS_INT128 to KconfigMasahiro Yamada
2018-10-22RISC-V: remove the unused return_to_handler exportChristoph Hellwig
2018-10-22RISC-V: Add futex support.Jim Wilson
2018-10-22RISC-V: Add FP register ptrace support for gdb.Jim Wilson
2018-10-22RISC-V: Mask out the F extension on systems without DPalmer Dabbelt
2018-10-22RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}Palmer Dabbelt
2018-10-22RISC-V: Show IPI statsAnup Patel
2018-10-22RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfoAnup Patel
2018-10-22RISC-V: Use Linux logical CPU number instead of hartidAtish Patra
2018-10-22RISC-V: Add logical CPU indexing for RISC-VAtish Patra
2018-10-22RISC-V: Use WRITE_ONCE instead of direct accessAtish Patra
2018-10-22RISC-V: Use mmgrab()Palmer Dabbelt
2018-10-22RISC-V: Rename im_okay_therefore_i_am to found_boot_cpuPalmer Dabbelt
2018-10-22RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt
2018-10-22RISC-V: Provide a cleaner raw_smp_processor_id()Palmer Dabbelt
2018-10-22RISC-V: Disable preemption before enabling interruptsAtish Patra
2018-10-22RISC-V: Comment on the TLB flush in smp_callin()Palmer Dabbelt
2018-10-22RISC-V: Filter ISA and MMU values in cpuinfoPalmer Dabbelt
2018-10-22RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}Palmer Dabbelt
2018-10-22RISC-V: No need to pass scause as arg to do_IRQ()Anup Patel
2018-10-22RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremapVincent Chen
2018-10-22RISC-V: Select GENERIC_LIB_UMODDI3 on RV32Zong Li
2018-10-22RISC-V: Use swiotlb on RV64 onlyZong Li
2018-10-22RISC-V: Build tishift only on 64-bitZong Li
2018-10-22Auto-detect whether a FPU existsAlan Kao
2018-10-22Allow to disable FPU supportAlan Kao
2018-10-22Cleanup ISA string settingAlan Kao
2018-10-22Refactor FPU code in signal setup/return proceduresAlan Kao
2018-10-22Extract FPU context operations from entry.SAlan Kao
2018-10-03signal: Remove the need for __ARCH_SI_PREABLE_SIZE and SI_PAD_SIZEEric W. Biederman
2018-10-02RISCV: Fix end PFN for low memoryAtish Patra
2018-09-24RISC-V: include linux/ftrace.h in asm-prototypes.hJames Cowgill