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path: root/arch/xtensa/boot/dts/csp.dts
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2016-09-19xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config.Scott Telford
Add module parameter xilinx_uartps.rx_trigger_level=32 to command line options for CSP to set Rx watermark for xuartps driver lower than the default value, to avoid UART overruns at 115200 bps. Signed-off-by: Scott Telford <stelford@cadence.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-09xtensa: Added Cadence CSP kernel configuration for XtensaScott Telford
Added defconfig, device tree and Xtensa variant header files for the Cadence Configurable System Platform "xt_lnx" processor configuration. Signed-off-by: Scott Telford <stelford@cadence.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>