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2014-07-23arm64: Convert bool ARM64_x_LEVELS to int ARM64_PGTABLE_LEVELSCatalin Marinas
Rather than having several Kconfig options, define int ARM64_PGTABLE_LEVELS which will be also useful in converting some of the pgtable macros. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Jungseok Lee <jungseoklee85@gmail.com>
2014-07-23arm64: mm: Implement 4 levels of translation tablesJungseok Lee
This patch implements 4 levels of translation tables since 3 levels of page tables with 4KB pages cannot support 40-bit physical address space described in [1] due to the following issue. It is a restriction that kernel logical memory map with 4KB + 3 levels (0xffffffc000000000-0xffffffffffffffff) cannot cover RAM region from 544GB to 1024GB in [1]. Specifically, ARM64 kernel fails to create mapping for this region in map_mem function since __phys_to_virt for this region reaches to address overflow. If SoC design follows the document, [1], over 32GB RAM would be placed from 544GB. Even 64GB system is supposed to use the region from 544GB to 576GB for only 32GB RAM. Naturally, it would reach to enable 4 levels of page tables to avoid hacking __virt_to_phys and __phys_to_virt. However, it is recommended 4 levels of page table should be only enabled if memory map is too sparse or there is about 512GB RAM. References ---------- [1]: Principles of ARM Memory Maps, White Paper, Issue C Signed-off-by: Jungseok Lee <jays.lee@samsung.com> Reviewed-by: Sungjinn Chung <sungjinn.chung@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Steve Capper <steve.capper@linaro.org> [catalin.marinas@arm.com: MEMBLOCK_INITIAL_LIMIT removed, same as PUD_SIZE] [catalin.marinas@arm.com: early_ioremap_init() updated for 4 levels] [catalin.marinas@arm.com: 48-bit VA depends on BROKEN until KVM is fixed] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Jungseok Lee <jungseoklee85@gmail.com>
2014-07-23arm64: Add 4 levels of page tables definition with 4KB pagesJungseok Lee
This patch adds hardware definition and types for 4 levels of translation tables with 4KB pages. Signed-off-by: Jungseok Lee <jays.lee@samsung.com> Reviewed-by: Sungjinn Chung <sungjinn.chung@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Jungseok Lee <jungseoklee85@gmail.com>
2014-07-23arm64: Introduce VA_BITS and translation level optionsJungseok Lee
This patch adds virtual address space size and a level of translation tables to kernel configuration. It facilicates introduction of different MMU options, such as 4KB + 4 levels, 16KB + 4 levels and 64KB + 3 levels, easily. The idea is based on the discussion with Catalin Marinas: http://www.spinics.net/linux/lists/arm-kernel/msg319552.html Signed-off-by: Jungseok Lee <jays.lee@samsung.com> Reviewed-by: Sungjinn Chung <sungjinn.chung@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Jungseok Lee <jungseoklee85@gmail.com>
2014-07-23arm64: Do not initialise the fixmap page tables in head.SCatalin Marinas
The early_ioremap_init() function already handles fixmap pte initialisation, so upgrade this to cover all of pud/pmd/pte and remove one page from swapper_pg_dir. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Jungseok Lee <jungseoklee85@gmail.com>
2014-07-23ARM: mvebu: fix return value check in armada_xp_pmsu_cpufreq_init()Wei Yongjun
In case of error, the function clk_get() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Link: https://lkml.kernel.org/r/1406038688-26417-1-git-send-email-weiyj_lk@163.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-23ARM: zynq: DT: Add GPIO nodeSoren Brinkmann
Add node describing Zynq's GPIO controller. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-07-23ARM: zynq: DT: Add XADC nodeSoren Brinkmann
Add node for the Xilinx A/D Converter. Cc: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-07-23ARM: mvebu: Add missing MDIO clock in Armada 375Ezequiel Garcia
In Armada 375 SoCs, the MDIO is handled by a separate orion-mdio driver, despite the register is contained within the "LMS" block of the network controller. Therefore we need to add the clock to the MDIO devicetree to prevent the controller from being accesed with its clock gated. This is needed, for instance, to be able to load the MDIO driver before the network driver. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1405961296-5846-7-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-23ARM: mvebu: Add ethernet aliases required by U-BootMarcin Wojtas
The vendor bootloader provided for Armada 375 boards expect an alias for the ethernet nodes, which is used to fixup the MAC address. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Link: https://lkml.kernel.org/r/1405961296-5846-6-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-23arm64: Create non-empty ZONE_DMA when DRAM starts above 4GBCatalin Marinas
ZONE_DMA is created to allow 32-bit only devices to access memory in the absence of an IOMMU. On systems where the memory starts above 4GB, it is expected that some devices have a DMA offset hardwired to be able to access the bottom of the memory. Linux currently supports DT bindings for the DMA offsets but they are not (easily) available early during boot. This patch tries to guess a DMA offset and assumes that ZONE_DMA corresponds to the 32-bit mask above the start of DRAM. Fixes: 2d5a5612bc (arm64: Limit the CMA buffer to 32-bit if ZONE_DMA) Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Mark Salter <msalter@redhat.com> Tested-by: Mark Salter <msalter@redhat.com> Tested-by: Anup Patel <anup.patel@linaro.org>
2014-07-23ARM: pxa: Add non device-tree timer link to clocksourceRobert Jarzmik
As clocksource pxa_timer was moved to clocksource framework, the pxa_timer initialization needs to be a bit amended, to pass the necessary informations to clocksource, ie : - the timer interrupt (mach specific) - the timer registers base (ditto) - the timer clockrate Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-07-23ARM: pxa: Add CLKSRC_OF dependencyRobert Jarzmik
Select CLKSRC_OF for PXA architectures. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-07-23clocksource: pxa: Move PXA timer to clocksource frameworkRobert Jarzmik
Move time.c from arch/arm/mach-pxa/time.c to drivers/clocksource/pxa_timer.c. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-07-23ARM: rockchip: Add cpu hotplug support for RK3XXX SoCsRomain Perier
Adds ability to shutdown all CPUs except the first one (since it might be special for a lot of platforms). It is now possible to use kexec which requires such a feature. Signed-off-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-07-23ARM: rockchip: select ARMv7 compiler flags for platsmp.oHeiko Stuebner
When compiling for multiplatform for both ARMv6 and ARMv7, the default compiler flags are for ARMv6, and the following cpu-hotplug change will fail with: /tmp/ccSFxfmI.s:68: Error: selected processor does not support ARM mode `isb ' /tmp/ccSFxfmI.s:74: Error: selected processor does not support ARM mode `isb ' /tmp/ccSFxfmI.s:75: Error: selected processor does not support ARM mode `dsb ' Fix this in a similar manner as in commit 9f0affcf3e21 "ARM: mvebu: Fix pmsu compilation when ARMv6 is selected", by specifying ARMv7 flags for platsmp.o. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-07-23ARM: OMAP2+: gpmc: fix gpmc_hwecc_bch_capable()Christoph Fritz
This patch adds bch8 ecc software fallback which is mostly used by omap3s because they lack hardware elm support. Fixes: 0611c41934ab35ce84dea34ab291897ad3cbc7be (ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms and ECC schemes) Cc: <stable@vger.kernel.org> # 3.15.x+ Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Reviewed-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-07-23arm64: Remove stray ARCH_HAS_OPP referenceMark Brown
A reference to ARCH_HAS_OPP was added in commit 333d17e56 (arm64: add ARCH_HAS_OPP to allow enabling OPP library) however this symbol is no longer needed after commit 049d595a4db3b3a (PM / OPP: Make OPP invisible to users in Kconfig). Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-07-23Merge branch 'omap-for-v3.17/mailbox' into omap-for-v3.17/socTony Lindgren
2014-07-23Merge tag 'for-v3.17/omap-hwmod-a' of ↵Tony Lindgren
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.17/soc OMAP hwmod data additions for v3.17. Most of these are DRA7xx-related, although one patch adds DSS hwmods for AM43xx. Basic build, boot, and PM test results are available here: http://www.pwsan.com/omap/testlogs/hwmod-a-v3.17/20140722143514/
2014-07-23powerpc/perf: Fix MMCR2 handling for EBBMichael Ellerman
In the recent commit b50a6c584bb4 "Clear MMCR2 when enabling PMU", I screwed up the handling of MMCR2 for tasks using EBB. We must make sure we set MMCR2 *before* ebb_switch_in(), otherwise we overwrite the value of MMCR2 that userspace may have written. That potentially breaks a task that uses EBB and manually uses MMCR2 for event freezing. Fixes: b50a6c584bb4 ("powerpc/perf: Clear MMCR2 when enabling PMU") Cc: stable@vger.kernel.org Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-07-23ARC: help gcc elide icache helper for !SMPVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-07-23ARC: move common ops for line/full cache into helpersVineet Gupta
INV cmd for dcache provides 2 modes discard or wback-before-discard. One is default and other needs to be set, if so desired. This is common for line-op/entire-cache-op. So refactor them out into a helper Doesn't affect generated code but paves way for any common micro-optimization. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-07-23ARC: cache boot reporting updatesVineet Gupta
* print aliasing or not, VIPT/PIPT etc * compress param storage using bitfields * more use of IS_ENABLED to de-uglify code Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-07-23ARC: [intc] mask/unmask can be hidden againVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-07-23ARC: [plat-arcfpga] No need for init_irq hackVineet Gupta
With all IRQs unmasked by default on all cores, it is no longer needed to unmask them explicitly. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-07-23ARC: [intc] don't mask all IRQ by defaultVineet Gupta
Hardware keeps them enabled on reset, and Linux needs to keep status quo. Any spurious interrupts will be reported/blocked by genirq. This helps remove a SMP IRQ quirk (next commit), where a peripheral IRQ is hard wired to core0, and request_irq()->unmask() happens on core1, keeping the IRQ masked on core0, needing an explicit unmask. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-07-23ARC: prune extra header includes from smp.cVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-07-23ARC: update some commentsVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-07-23ARC: [SMP] unify cpu private IRQ requests (TIMER/IPI)Vineet Gupta
The current cpu-private IRQ registration is ugly as it requires need to expose arch_unmask_irq() outside of intc code. So switch to percpu IRQ APIs: -request_percpu_irq [boot core] -enable_percpu_irq [all cores] Encapsulated in helper arc_request_percpu_irq() Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-07-23ARM: shmobile: r8a7791: Fix SD2CKCR register addressShinobu Uehara
59e79895b95892863617ce630fbda467f2470575 (ARM: shmobile: r8a7791: Add clocks) added r8a7791 SD clocks when v3.14. 2c60a7df72711fb8b4be1e6aa651ab166a8931bc (ARM: shmobile: Add SDHI devices for Koelsch DTS) enabled SD on r8a7791 Koelsch when v3.15. 1299df03d7191ab4356c995dde8b912d3c8922e9 (ARM: shmobile: henninger: add SDHI0/2 DT support) enable SD on r8a7791 Henninger when v3.16. But r8a7791 SD clock had wrong address. This patch fixup it. [Kuninori Morimoto: tidyup for upstreaming] Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-07-23ARM: EXYNOS: Move cpufreq and cpuidle device registration to init_machinePankaj Dubey
As exynos_cpuidle_init() and exynos_cpufreq_init() functions have just one line of code for registering platform devices. So we can move them to exynos_dt_machine_init() and remove exynos_cpuidle_init() and exynos_cpufreq_init(). This will help in reducing lines of code in exynos.c, making it more clean. Suggested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-23ARM: EXYNOS: Refactored code for using PMU address via DTPankaj Dubey
Under "arm/mach-exynos" many files are using PMU register offsets. Since we have added support for accessing PMU base address via DT, now we can remove PMU mapping from exynosX_iodesc. Let's convert all these access using iomapped address. This will help us in removing static mapping of PMU base address as well as help in reducing dependency over machine header files. Thus helping for migration of PMU implementation from machine to driver folder which can be reused for ARM64 based SoC. Also as we have removed static mappings from "regs-pmu.h" it does not need map.h anymore. But "platsmp.c" needed this and till now it got included indirectly. So lets move header inclusion of "mach/map.h" from "regs-pmu.h" to "platsmp.c". Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-23ARM: EXYNOS: Support cluster power off on exynos5420/5800Abhilash Kesavan
Turning off a cluster when all 4 cores of the cluster are powered off saves power significantly. Powering off the A15 L2 alone gives around 100mW in savings. Add support for powering off the A15/A7 clusters on exynos5420/5800. The patch enables specific register bits which ensure that: - cluster L2 will be turned on before the first man is powered up. - last man will be turned off before the cluster L2 is turned off. - core is powered down before powering it up. Remove the exynos_cluster_power_control function completely as we can rely on the above mentioned bits rather than polling the cluster power status register. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Nicolas Pitre <nico@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-23Merge branch 'v3.17-next/cpuidle-exynos' into v3.17-next/power-exynosKukjin Kim
2014-07-23Merge branch 'v3.17-next/cleanup-samsung' into v3.17-next/power-exynosKukjin Kim
2014-07-23ACPICA: Linux: Add support to exclude <asm/acenv.h> inclusion.Lv Zheng
The forthcoming patch will make <acpi/acpi.h> to be visible to all kernel source code. Thus for the architectures that do not support ACPI and haven't implemented <asm/acenv.h>, we need to make it excluded. Signed-off-by: Lv Zheng <lv.zheng@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2014-07-23PM / OPP: Remove ARCH_HAS_OPPMark Brown
Since the OPP layer is a kernel library which has been converted to be directly selectable by its callers rather than user selectable and requiring architectures to enable it explicitly the ARCH_HAS_OPP symbol has become redundant and can be removed. Do so. Signed-off-by: Mark Brown <broonie@linaro.org> Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Shawn Guo <shawn.guo@freescale.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2014-07-22acpi, apei, ghes: Factor out ioremap virtual memory for IRQ and NMI context.Tomasz Nowicki
GHES currently maps two pages with atomic_ioremap. From now on, NMI is architectural depended so there is no need to allocate an NMI page for platforms without NMI support. To make it possible to not use a second page, swap the existing page order so that the IRQ context page is first, and the optional NMI context page is second. Then, use HAVE_ACPI_APEI_NMI to decide how many pages are to be allocated. Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> Acked-by: Borislav Petkov <bp@suse.de> Signed-off-by: Tony Luck <tony.luck@intel.com>
2014-07-22acpi, apei, ghes: Make NMI error notification to be GHES architecture extension.Tomasz Nowicki
Currently APEI depends on x86 architecture. It is because of NMI hardware error notification of GHES which is currently supported by x86 only. However, many other APEI features can be still used perfectly by other architectures. This commit adds two symbols: 1. HAVE_ACPI_APEI for those archs which support APEI. 2. HAVE_ACPI_APEI_NMI which is used for NMI code isolation in ghes.c file. NMI related data and functions are grouped so they can be wrapped inside one #ifdef section. Appropriate function stubs are provided for !NMI case. Note there is no functional changes for x86 due to hard selected HAVE_ACPI_APEI and HAVE_ACPI_APEI_NMI symbols. Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> Acked-by: Borislav Petkov <bp@suse.de> Signed-off-by: Tony Luck <tony.luck@intel.com>
2014-07-22apei, mce: Factor out APEI architecture specific MCE calls.Tomasz Nowicki
This commit abstracts MCE calls and provides weak corresponding default implementation for those architectures which do not need arch specific actions. Each platform willing to do additional architectural actions should provides desired function definition. It allows us to avoid wrap code into #ifdef in generic code and prevent new platform from introducing dummy stub function too. Initially, there are two APEI arch-specific calls: - arch_apei_enable_cmcff() - arch_apei_report_mem_error() Both interact with MCE driver for X86 architecture. Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> Acked-by: Borislav Petkov <bp@suse.de> Signed-off-by: Tony Luck <tony.luck@intel.com>
2014-07-22Merge branch 'mvebu/soc-cpufreq' into mvebu/socJason Cooper
2014-07-22ARM: DRA7: hwmod: Add data for RTCLokesh Vutla
Add hwmod data for RTC Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-22arm: dra7xx: Add hwmod data for MDIO and CPSWMugunthan V N
Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC Cc: Rajendra Nayak <rnayak@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-22arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystemsKishon Vijay Abraham I
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC. Cc: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-22arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phyKishon Vijay Abraham I
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC. Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro for pcie1 phy and pcie2 phy. Cc: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-22ARM: DRA7: hwmod: Add OCP2SCP3 moduleRoger Quadros
This module is needed for the SATA and PCIe PHYs. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-22Merge tag 'sti-defconfig-for-v3.17-1' of ↵Olof Johansson
git://git.stlinux.com/devel/kernel/linux-sti into next/defconfig Merge "ARM: STi: defconfig changes for v3.17" from Maxime Coquelin: STi defconfig updates for v3.17 - Enable ST's Thermal controller driver - Enable ST's Keyscan driver - Enable ST's MiPHY365 Phy driver for STiH416 SATA & PCIe - Enable ST's AHCI driver. * tag 'sti-defconfig-for-v3.17-1' of git://git.stlinux.com/devel/kernel/linux-sti: ARM: multi_v7_defconfig: Enable MiPHY365x - ST's Generic (SATA & PCIe) PHY ARM: multi_v7_defconfig: Enable ST's (S)ATA driver ARM: multi_v7_defconfig: add ST Keyscan driver ARM: update multi_v7_defconfig for STI ARM: multi_v7_defconfig: Configure in ST's Thermal Controller + Linux 3.16-rc6 Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-22arm: mediatek: add dts for Aquaris5 mobile phoneMatthias Brugger
The Aquaris5 is a mobile phone based on the MT6589 SoC. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2014-07-22arm: add basic support for Mediatek MT6589 boardsMatthias Brugger
This adds a generic devicetree board file and a dtsi for boards based on MT6589 SoCs from Mediatek. Apart from the generic parts (gic, clocks) the only component currently supported are the timers. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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