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2013-02-17MIPS: ralink: adds irq codeJohn Crispin
All of the Ralink Wifi SoC currently supported by this series share the same interrupt controller (INTC). Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4890/
2013-02-17MIPS: ralink: adds include filesJohn Crispin
Before we start adding the platform code we add the common include files. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4893/
2013-02-17MIPS: ath79: simplify MISC IRQ handlingGabor Juhos
The current code uses multiple if statements for demultiplexing the different interrupt sources. Additionally, the MISC interrupt controller has 32 interrupt sources and the current code does not handles all of them. Get rid of the if statements and process all interrupt sources in a loop to fix these issues. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4874/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: ath79: simplify ath79_gpio_function_* routinesGabor Juhos
Make ath79_gpio_function_{en,dis}able to be wrappers around ath79_gpio_function_setup. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4871/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: ath79: fix GPIO function selection for AR934x SoCsGabor Juhos
GPIO function selection is not working on the AR934x SoCs because the offset of the function selection register is different on those. Add a helper routine which returns the correct register address based on the SoC type, and use that in the 'ath79_gpio_function_*' routines. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4870/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Add new GIC clocksource.Steven J. Hill
Add new clocksource that uses the counter present on the MIPS Global Interrupt Controller. Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4681/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: dsp: Simplify the DSP macros.Steven J. Hill
Simplify the DSP macros for vanilla (non-microMIPS) kernels and toolchains that do not support the DSP ASEs. Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4687/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: dsp: Support toolchains without DSP ASE and microMIPS.Steven J. Hill
Add macros to support the DSP ASE with microMIPS kernels when the toolchain does not have support. Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4686/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: dsp: Add assembler support for DSP ASEs.Steven J. Hill
Newer toolchains support the DSP and DSP Rev2 instructions. This patch performs a check for that support and adds compiler and assembler flags for only the files that need use those instructions. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4752/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Add support for the M14KEc core.Steven J. Hill
Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4682/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Clean-ups for MIPS Technologies Inc. generic header file.Steven J. Hill
Clean up standard header text and remove unused #define. Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4703/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: PCI: Multi-node PCI support for Netlogic XLPJayachandran C
On a multi-chip XLP board, each node can have 4 PCIe links. Update XLP PCI code to initialize PCIe on all the nodes. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4803/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: Fix for quad-XLP bootJayachandran C
On multi-chip boards, the first core on slave SoCs may take much more time to wakeup. Add code to wait for the core to come up before proceeding with the rest of the boot up. Update xlp_wakeup_core to also skip the boot node and the boot CPU initialization which is already complete. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4783/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: use preset loops per jiffyJayachandran C
Doing calibrate delay on a hardware thread will be inaccurate since it depends on the load on other threads in the core. It will also slow down the boot process when done for 128 hardware threads. Switch to a pre-computed loops per jiffy based on the core frequency. The value is computed based on the core frequency and roughly matches the value calculated by calibrate_delay(). Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4791/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: No hazards needed for XLR/XLSJayachandran C
TLB and COP0 hazards are handled in hardware for Netlogic XLR/XLS SoCs. Update hazards.h to pick more optimal set of definitions when compiling for XLR/XLS. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4788/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: PCI: Prevent hang on XLP reg readJayachandran C
Reading PCI extended register at 0x255 on a bridge will hang if there is no device connected on the link. Make PCI read routine skip this register. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4789/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: Use PIC timer as a clocksourceJayachandran C
The XLR/XLS/XLP PIC has a 8 countdown timers which run at the PIC frequencey. One of these can be used as a clocksource to provide timestamps that is common across cores. This can be used in place of the count/compare clocksource which is per-CPU. On XLR/XLS PIC registers are 32-bit, so we just use the lower 32-bits of the PIC counter. On XLP, the whole 64-bit can be used. Provide common macros and functions for PIC timer registers on XLR/XLS and XLP, and use them to register a PIC clocksource. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4786/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: Split XLP L1 i-cache among threadsJayachandran C
Since we now use r4k cache code for Netlogic XLP, it is better to split L1 icache among the active threads, so that threads won't step on each other while flushing icache. The L1 dcache is already split among the threads in the core. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4787/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: PCI: Byteswap not needed in little-endian modeJayachandran C
Rename function xlp_enable_pci_bswap() to xlp_config_pci_bswap(), which is a better description for its functionality. When compiled in big-endian mode, xlp_config_pci_bswap() will configure the PCIe links to byteswap. In little-endian mode, no swap configuration is needed for the PCIe controller, and the function is empty. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4802/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: Optimize EIMR/EIRR accesses in 32-bitJayachandran C
Provide functions ack_c0_eirr(), set_c0_eimr(), clear_c0_eimr() and read_c0_eirr_and_eimr() that do the EIMR and EIRR operations and update the interrupt handling code to use these functions. Also, use the EIMR register functions to mask interrupts in the irq code. The 64-bit interrupt request and mask registers (EIRR and EIMR) are accessed when the interrupts are off, and the common operations are to set or clear a bit in these registers. Using the 64-bit c0 access functions for these operations is not optimal in 32-bit, because it will disable/restore interrupts and split/join the 64-bit value during each register access. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4790/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: add XLS6xx to FMN configJayachandran C
Add support for XLS6xx CPUs to the Fast Message Network (FMN) configuration. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4785/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: lantiq: rework external irq codeJohn Crispin
This code makes the irqs used by the EIU loadable from the DT. Additionally we add a helper that allows the pinctrl layer to map external irqs to real irq numbers. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4818/
2013-02-17MIPS: lantiq: improve pci reset gpio handlingJohn Crispin
We need to make sure that the reset gpio is available and also set a sane default state. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4817/
2013-02-17MIPS: lantiq: add GPHY clock gate bitsJohn Crispin
Explicitly enable the clock gate of the internal GPHYs found on xrx200. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4816/
2013-02-17MIPS: lantiq: adds static clock for PP32John Crispin
The Lantiq DSL SoCs have an internal networking processor. Add code to read the static clock rate. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4815/
2013-02-17MIPS: lantiq: trivial typo fixJohn Crispin
"nodes" is written with a single "s" Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4814/
2013-02-17MIPS: show correct cpu name for 24KEcJohn Crispin
Make sure 24KEc is properly identified inside /proc/cpuinfo Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: use fallback sprom var for board_{rev,type}Hauke Mehrtens
An SoC normally do not define path variables for board_rev and board_type and the Broadcom SDK also uses the nvram values without a prefix in such cases. Do the same to fill these sprom attributes from nvram and do not leave them empty, because brcmsmac do not like this. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4679/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: select NO_EXCEPT_FILLHauke Mehrtens
The kernel is loaded to 0x80001000 so there is some space left for the exception handlers and the kernel do not have to reserve some extra space for them. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4747/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: select BOOT_RAWHauke Mehrtens
All the boot loaders I have seen are booting the kernel in raw mode by default. CFE seems to support elf kernel images too, but the default case is raw for the devices I know of. Select this option to make the kernel boot on most of the devices with the default options. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4746/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: trim the nvram values for parsingHauke Mehrtens
Some nvram values on some devices have a newline character at the end of the value, that caused read errors. Trim the string before reading the number. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4745/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: add bcm47xx prefix in front of nvram function namesHauke Mehrtens
The nvram functions are exported and used by some normal drivers. To prevent name clashes with ofter parts of the kernel code add a bcm47xx_ prefix in front of the function names and the header file name. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4744/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: handle different nvram sizesHauke Mehrtens
The old code just worked for nvram with a size of 0x8000 bytes. This patch adds support for reading nvram from partitions of 0xF000 and 0x10000 bytes. There is just 32KB space for the nvram, but most devices do not use the full size and this code reads the first 32KB in that case and prints a warning. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4743/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: rename early_nvram_init to nvram_initHauke Mehrtens
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4742/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: nvram add nand flash supportHauke Mehrtens
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4741/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: return error when init of nvram failedHauke Mehrtens
This makes it possible to handle the case of not being able to read the nvram ram. This could happen when the code searching for the specific flash chip have not run jet. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4740/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: use common error codes in nvram readsHauke Mehrtens
Instead of using our own error codes use some common codes. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4739/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: bcm47xx: separate functions finding flash window addrRafał Miłecki
Also check if parallel flash is present at all before accessing it and add support for serial flash on BCMA bus. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4738/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-09Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds
Pull ARM fixes from Russell King: "I was going to hold these off until v3.8 was out, and send them with a stable tag, but as everyone else is pushing much bigger fixes which Linus is accepting, let's save people from the hastle of having to patch v3.8 back into working or use a stable kernel. Looking at the diffstat, this really is high value for its size; this is miniscule compared to how the -rc6 to tip diffstat currently looks. So, four patches in this set: - Punit Agrawal reports that the kernel no longer boots on MPCore due to a new assumption made in the GIC code which isn't true of earlier GIC designs. This is the biggest change in this set. - Punit's boot log also revealed a bunch of WARN_ON() dumps caused by the DT-ification of the GIC support without fixing up non-DT Realview - which now sees a greater number of interrupts than it did before. - A fix for the DMA coherent code from Marek which uses the wrong check for atomic allocations; this can result in spinlock lockups or other nasty effects. - A fix from Will, which will affect all Android based platforms if not applied (which use the 2G:2G VM split) - this causes particularly 'make' to misbehave unless this bug is fixed." * 'fixes' of git://git.linaro.org/people/rmk/linux-arm: ARM: 7641/1: memory: fix broken mmap by ensuring TASK_UNMAPPED_BASE is aligned ARM: DMA mapping: fix bad atomic test ARM: realview: ensure that we have sufficient IRQs available ARM: GIC: fix GIC cpumask initialization
2013-02-08ARM: 7641/1: memory: fix broken mmap by ensuring TASK_UNMAPPED_BASE is alignedWill Deacon
We have received multiple reports of mmap failures when running with a 2:2 vm split. These manifest as either -EINVAL with a non page-aligned address (ending 0xaaa) or a SEGV, depending on the application. The issue is commonly observed in children of make, which appears to use bottom-up mmap (assumedly because it changes the stack rlimit). Further investigation reveals that this regression was triggered by 394ef6403abc ("mm: use vm_unmapped_area() on arm architecture"), whereby TASK_UNMAPPED_BASE is no longer page-aligned for bottom-up mmap, causing get_unmapped_area to choke on misaligned addressed. This patch fixes the problem by defining TASK_UNMAPPED_BASE in terms of TASK_SIZE and explicitly aligns the result to 16M, matching the other end of the heap. Acked-by: Nicolas Pitre <nico@linaro.org> Reported-by: Steve Capper <steve.capper@arm.com> Reported-by: Jean-Francois Moine <moinejf@free.fr> Reported-by: Christoffer Dall <cdall@cs.columbia.edu> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-02-08ARM: DMA mapping: fix bad atomic testRussell King
Realview fails to boot with this warning: BUG: spinlock lockup suspected on CPU#0, init/1 lock: 0xcf8bde10, .magic: dead4ead, .owner: init/1, .owner_cpu: 0 Backtrace: [<c00185d8>] (dump_backtrace+0x0/0x10c) from [<c03294e8>] (dump_stack+0x18/0x1c) r6:cf8bde10 r5:cf83d1c0 r4:cf8bde10 r3:cf83d1c0 [<c03294d0>] (dump_stack+0x0/0x1c) from [<c018926c>] (spin_dump+0x84/0x98) [<c01891e8>] (spin_dump+0x0/0x98) from [<c0189460>] (do_raw_spin_lock+0x100/0x198) [<c0189360>] (do_raw_spin_lock+0x0/0x198) from [<c032cbac>] (_raw_spin_lock+0x3c/0x44) [<c032cb70>] (_raw_spin_lock+0x0/0x44) from [<c01c9224>] (pl011_console_write+0xe8/0x11c) [<c01c913c>] (pl011_console_write+0x0/0x11c) from [<c002aea8>] (call_console_drivers.clone.7+0xdc/0x104) [<c002adcc>] (call_console_drivers.clone.7+0x0/0x104) from [<c002b320>] (console_unlock+0x2e8/0x454) [<c002b038>] (console_unlock+0x0/0x454) from [<c002b8b4>] (vprintk_emit+0x2d8/0x594) [<c002b5dc>] (vprintk_emit+0x0/0x594) from [<c0329718>] (printk+0x3c/0x44) [<c03296dc>] (printk+0x0/0x44) from [<c002929c>] (warn_slowpath_common+0x28/0x6c) [<c0029274>] (warn_slowpath_common+0x0/0x6c) from [<c0029304>] (warn_slowpath_null+0x24/0x2c) [<c00292e0>] (warn_slowpath_null+0x0/0x2c) from [<c0070ab0>] (lockdep_trace_alloc+0xd8/0xf0) [<c00709d8>] (lockdep_trace_alloc+0x0/0xf0) from [<c00c0850>] (kmem_cache_alloc+0x24/0x11c) [<c00c082c>] (kmem_cache_alloc+0x0/0x11c) from [<c00bb044>] (__get_vm_area_node.clone.24+0x7c/0x16c) [<c00bafc8>] (__get_vm_area_node.clone.24+0x0/0x16c) from [<c00bb7b8>] (get_vm_area_caller+0x48/0x54) [<c00bb770>] (get_vm_area_caller+0x0/0x54) from [<c0020064>] (__alloc_remap_buffer.clone.15+0x38/0xb8) [<c002002c>] (__alloc_remap_buffer.clone.15+0x0/0xb8) from [<c0020244>] (__dma_alloc+0x160/0x2c8) [<c00200e4>] (__dma_alloc+0x0/0x2c8) from [<c00204d8>] (arm_dma_alloc+0x88/0xa0)[<c0020450>] (arm_dma_alloc+0x0/0xa0) from [<c00beb00>] (dma_pool_alloc+0xcc/0x1a8) [<c00bea34>] (dma_pool_alloc+0x0/0x1a8) from [<c01a9d14>] (pl08x_fill_llis_for_desc+0x28/0x568) [<c01a9cec>] (pl08x_fill_llis_for_desc+0x0/0x568) from [<c01aab8c>] (pl08x_prep_slave_sg+0x258/0x3b0) [<c01aa934>] (pl08x_prep_slave_sg+0x0/0x3b0) from [<c01c9f74>] (pl011_dma_tx_refill+0x140/0x288) [<c01c9e34>] (pl011_dma_tx_refill+0x0/0x288) from [<c01ca748>] (pl011_start_tx+0xe4/0x120) [<c01ca664>] (pl011_start_tx+0x0/0x120) from [<c01c54a4>] (__uart_start+0x48/0x4c) [<c01c545c>] (__uart_start+0x0/0x4c) from [<c01c632c>] (uart_start+0x2c/0x3c) [<c01c6300>] (uart_start+0x0/0x3c) from [<c01c795c>] (uart_write+0xcc/0xf4) [<c01c7890>] (uart_write+0x0/0xf4) from [<c01b0384>] (n_tty_write+0x1c0/0x3e4) [<c01b01c4>] (n_tty_write+0x0/0x3e4) from [<c01acfe8>] (tty_write+0x144/0x240) [<c01acea4>] (tty_write+0x0/0x240) from [<c01ad17c>] (redirected_tty_write+0x98/0xac) [<c01ad0e4>] (redirected_tty_write+0x0/0xac) from [<c00c371c>] (vfs_write+0xbc/0x150) [<c00c3660>] (vfs_write+0x0/0x150) from [<c00c39c0>] (sys_write+0x4c/0x78) [<c00c3974>] (sys_write+0x0/0x78) from [<c0014460>] (ret_fast_syscall+0x0/0x3c) This happens because the DMA allocation code is not respecting atomic allocations correctly. GFP flags should not be tested for GFP_ATOMIC to determine if an atomic allocation is being requested. GFP_ATOMIC is not a flag but a value. The GFP bitmask flags are all prefixed with __GFP_. The rest of the kernel tests for __GFP_WAIT not being set to indicate an atomic allocation. We need to do the same. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-02-08ARM: realview: ensure that we have sufficient IRQs availableRussell King
Realview EB with a rev B MPcore tile results in lots of warnings at boot because it can't allocate enough IRQs. Fix this by increasing the number of available IRQs. WARNING: at /home/rmk/git/linux-rmk/arch/arm/common/gic.c:757 gic_init_bases+0x12c/0x2ec() Cannot allocate irq_descs @ IRQ96, assuming pre-allocated Modules linked in: Backtrace: [<c00185d8>] (dump_backtrace+0x0/0x10c) from [<c03294e8>] (dump_stack+0x18/0x1c) r6:000002f5 r5:c042c62c r4:c044ff40 r3:c045f240 [<c03294d0>] (dump_stack+0x0/0x1c) from [<c00292c8>] (warn_slowpath_common+0x54/0x6c) [<c0029274>] (warn_slowpath_common+0x0/0x6c) from [<c0029384>] (warn_slowpath_fmt+0x38/0x40) [<c002934c>] (warn_slowpath_fmt+0x0/0x40) from [<c042c62c>] (gic_init_bases+0x12c/0x2ec) [<c042c500>] (gic_init_bases+0x0/0x2ec) from [<c042cdc8>] (gic_init_irq+0x8c/0xd8) [<c042cd3c>] (gic_init_irq+0x0/0xd8) from [<c042827c>] (init_IRQ+0x1c/0x24) [<c0428260>] (init_IRQ+0x0/0x24) from [<c04256c8>] (start_kernel+0x1a4/0x300) [<c0425524>] (start_kernel+0x0/0x300) from [<70008070>] (0x70008070) ---[ end trace 1b75b31a2719ed1c ]--- ------------[ cut here ]------------ WARNING: at /home/rmk/git/linux-rmk/kernel/irq/irqdomain.c:234 irq_domain_add_legacy+0x80/0x140() Modules linked in: Backtrace: [<c00185d8>] (dump_backtrace+0x0/0x10c) from [<c03294e8>] (dump_stack+0x18/0x1c) r6:000000ea r5:c0081a38 r4:00000000 r3:c045f240 [<c03294d0>] (dump_stack+0x0/0x1c) from [<c00292c8>] (warn_slowpath_common+0x54/0x6c) [<c0029274>] (warn_slowpath_common+0x0/0x6c) from [<c0029304>] (warn_slowpath_null+0x24/0x2c) [<c00292e0>] (warn_slowpath_null+0x0/0x2c) from [<c0081a38>] (irq_domain_add_legacy+0x80/0x140) [<c00819b8>] (irq_domain_add_legacy+0x0/0x140) from [<c042c64c>] (gic_init_bases+0x14c/0x2ec) [<c042c500>] (gic_init_bases+0x0/0x2ec) from [<c042cdc8>] (gic_init_irq+0x8c/0xd8) [<c042cd3c>] (gic_init_irq+0x0/0xd8) from [<c042827c>] (init_IRQ+0x1c/0x24) [<c0428260>] (init_IRQ+0x0/0x24) from [<c04256c8>] (start_kernel+0x1a4/0x300) [<c0425524>] (start_kernel+0x0/0x300) from [<70008070>] (0x70008070) ---[ end trace 1b75b31a2719ed1d ]--- ------------[ cut here ]------------ WARNING: at /home/rmk/git/linux-rmk/arch/arm/common/gic.c:762 gic_init_bases+0x170/0x2ec() Modules linked in: Backtrace: [<c00185d8>] (dump_backtrace+0x0/0x10c) from [<c03294e8>] (dump_stack+0x18/0x1c) r6:000002fa r5:c042c670 r4:00000000 r3:c045f240 [<c03294d0>] (dump_stack+0x0/0x1c) from [<c00292c8>] (warn_slowpath_common+0x54/0x6c) [<c0029274>] (warn_slowpath_common+0x0/0x6c) from [<c0029304>] (warn_slowpath_null+0x24/0x2c) [<c00292e0>] (warn_slowpath_null+0x0/0x2c) from [<c042c670>] (gic_init_bases+0x170/0x2ec) [<c042c500>] (gic_init_bases+0x0/0x2ec) from [<c042cdc8>] (gic_init_irq+0x8c/0xd8) [<c042cd3c>] (gic_init_irq+0x0/0xd8) from [<c042827c>] (init_IRQ+0x1c/0x24) [<c0428260>] (init_IRQ+0x0/0x24) from [<c04256c8>] (start_kernel+0x1a4/0x300) [<c0425524>] (start_kernel+0x0/0x300) from [<70008070>] (0x70008070) ---[ end trace 1b75b31a2719ed1e ]--- Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-02-08ARM: GIC: fix GIC cpumask initializationRussell King
Punit Agrawal reports: > I was trying to boot 3.8-rc5 on Realview EB 11MPCore using > realview-smp_defconfig as a starting point but the kernel failed to > progress past the log below (config attached). > > Pawel suggested I try reverting 384a290283f - "ARM: gic: use a private > mapping for CPU target interfaces" that you've authored. With this > commit reverted the kernel boots. > > I am not quite sure why the commit breaks 11MPCore but Pawel (cc'd) > might be able to shed light on that. Some early GIC implementations return zero for the first distributor CPU routing register. This means we can't rely on that telling us which CPU interface we're connected to. We know that these platforms implement PPIs for IRQs 29-31 - but we shouldn't assume that these will always be populated. So, instead, scan for a non-zero CPU routing register in the first 32 IRQs and use that as our CPU mask. Reported-by: Punit Agrawal <punit.agrawal@arm.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-02-08Merge tag 'pinctrl-for-v3.8-late' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull late pinctrl fixes from Linus Walleij: "Two patches appeared as of late, one was completely news to me, the other one was rotated in -next for the next merge window but turned out to be a showstopper. - Exynos Kconfig fixup - SIRF DT translation bug" * tag 'pinctrl-for-v3.8-late' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: sirf: replace of_gpio_simple_xlate by sirf specific of_xlate pinctrl: exynos: change PINCTRL_EXYNOS option
2013-02-06Merge branch 'fixes-for-v3.8-rc7' of ↵Linus Torvalds
git://git.linaro.org/people/mszyprowski/linux-dma-mapping Pull DMA mapping fixes from Marek Szyprowski: "This pull request contains important bugfix patches for 9 architectures, which finally fixes broken allmodconfig builds introduced in v3.8-rc1. Those architectures don't use dma_map_ops based implementation and require manual update or additional dummy implementations of the missing new dma-mapping api functions: dma_mmap_coherent and dma_get_sgtable." * 'fixes-for-v3.8-rc7' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping: xtensa: Provide dummy dma_mmap_coherent() and dma_get_sgtable() parisc: Provide dummy dma_mmap_coherent() and dma_get_sgtable() mn10300: Provide dummy dma_mmap_coherent() and dma_get_sgtable() m68k: Provide dma_mmap_coherent() and dma_get_sgtable() frv: Provide dummy dma_mmap_coherent() and dma_get_sgtable() cris: Provide dma_mmap_coherent() and dma_get_sgtable() c6x: Provide dummy dma_mmap_coherent() and dma_get_sgtable() blackfin: Provide dma_mmap_coherent() and dma_get_sgtable() avr32: Provide dma_mmap_coherent() and dma_get_sgtable()
2013-02-05pinctrl: exynos: change PINCTRL_EXYNOS optionKukjin Kim
Since pinctrl-exynos can support exynos4 and exynos5 so changed the option name to PINCTRL_EXYNOS for more clarity. Cc: Thomas Abraham <Thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-05Merge branch 'x86-urgent-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Ingo Molnar: "Three small fixlets" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/intel/cacheinfo: Shut up annoying warning x86, doc: Boot protocol 2.12 is in 3.8 x86-64: Replace left over sti/cli in ia32 audit exit code
2013-02-05Merge branch 'perf-urgent-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull perf fixes from Ingo Molnar: "Three fixlets and two small (and low risk) hw-enablement changes" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf: Fix event group context move x86/perf: Add IvyBridge EP support perf/x86: Fix P6 driver section warning arch/x86/tools/insn_sanity.c: Identify source of messages perf/x86: Enable Intel Lincroft/Penwell/Cloverview Atom support
2013-02-04x86/intel/cacheinfo: Shut up annoying warningBorislav Petkov
I've been getting the following warning when doing randbuilds since forever. Now it finally pissed me off just the perfect amount so that I can fix it. arch/x86/kernel/cpu/intel_cacheinfo.c:489:27: warning: ‘cache_disable_0’ defined but not used [-Wunused-variable] arch/x86/kernel/cpu/intel_cacheinfo.c:491:27: warning: ‘cache_disable_1’ defined but not used [-Wunused-variable] arch/x86/kernel/cpu/intel_cacheinfo.c:524:27: warning: ‘subcaches’ defined but not used [-Wunused-variable] It happens because in randconfigs where CONFIG_SYSFS is not set, the whole sysfs-interface to L3 cache index disabling is remaining unused and gcc correctly warns about it. Make it optional, depending on CONFIG_SYSFS too, as is the case with other sysfs-related machinery in this file. Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Andreas Herrmann <andreas.herrmann3@amd.com> Link: http://lkml.kernel.org/r/1359969195-27362-1-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
2013-02-04Merge branch 'merge' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc Pull powerpc update from Benjamin Herrenschmidt: "Just so that you don't get too bored on your Island here's a patch for 3.8 fixing a nasty bug that affects the new 64T support that was merged in 3.7. Please apply whenever you have a chance (and an internet connection!)" * 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc/mm: Fix hash computation function
generated by cgit (git 2.34.1) at 2025-06-02 02:07:30 +0000