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AgeCommit message (Expand)Author
2015-09-03MIPS: Refactor dumping of TLB registers for r3k/r4kJames Hogan
2015-09-03MIPS: math-emu: Emulate missing BC1{EQ,NE}Z instructionsMarkos Chandras
2015-09-03MIPS: math-emu: Allow m{f,t}hc emulation on MIPS R6Markos Chandras
2015-09-03MIPS: math-emu: Fix indentationMarkos Chandras
2015-09-03MIPS: cp1emu: Fix closing bracket for the d_fmt caseMarkos Chandras
2015-09-03MIPS: Kconfig: Drop the EXPERIMENTAL tag from MIPS R6Markos Chandras
2015-09-03MIPS: Treat CP1 control registers as unsigned ints.Ralf Baechle
2015-09-03MIPS: Use unsigned int when reading CP0 registersChris Packham
2015-09-03MIPS: malta: Use generic platform_maar_initPaul Burton
2015-09-03MIPS: mm: default platform_maar_init using bootmem dataPaul Burton
2015-09-03MIPS: MSA unaligned memory access supportLeonid Yegoshin
2015-09-03MIPS: Introduce accessors for MSA vector registersPaul Burton
2015-09-03MIPS: Declare MSA MI10 instruction formatsLeonid Yegoshin
2015-09-03MIPS: Remove "__weak" definition from arch-specific linkage.hBjorn Helgaas
2015-09-03MIPS: Remove "weak" from mips_cdmm_phys_base() declarationBjorn Helgaas
2015-09-03MIPS: Remove "weak" from get_c0_fdc_int() declarationBjorn Helgaas
2015-09-03MIPS: Remove "weak" from get_c0_compare_int() declarationBjorn Helgaas
2015-08-26MIPS: MT: Remove "weak" from vpe_run() declarationBjorn Helgaas
2015-08-26MIPS: VPE: Exit vpe_release() early if vpe_run() isn't definedBjorn Helgaas
2015-08-26MIPS: Remove "weak" from platform_maar_init() declarationBjorn Helgaas
2015-08-26MIPS: CPC: Remove "weak" from mips_cpc_phys_base() and make it staticBjorn Helgaas
2015-08-26MIPS: Drop CONFIG_RUNTIME_DEBUG & debug.hPaul Burton
2015-08-26MIPS: ops-emma2rh: Drop nonsensical db_assertPaul Burton
2015-08-26MIPS: rt3883: Prepare rt3883_pci_irq_handler for irq argument removalThomas Gleixner
2015-08-26MIPS: netlogic: Prepare ipi handlers for irq argument removalThomas Gleixner
2015-08-26MIPS: octeon: Replace the homebrewn flow handlerThomas Gleixner
2015-08-26MIPS: ath91: Remove pointless irqdisable/enableThomas Gleixner
2015-08-26MIPS: alchemy: Remove pointless irqdisable/enableThomas Gleixner
2015-08-26MIPS: bcm63xx: Use irq_set_handler_locked()Thomas Gleixner
2015-08-26MIPS: alchemy: Use irq_set_chip_handler_name_locked()Thomas Gleixner
2015-08-26MIPS: irq: Use access helper irq_data_get_affinity_mask()Jiang Liu
2015-08-26MIPS: pci-rt3883: Consolidate chained IRQ handler install/removeThomas Gleixner
2015-08-26MIPS: pci-ar724x: Consolidate chained IRQ handler install/removeThomas Gleixner
2015-08-26MIPS: pci-ar71xx: Consolidate chained IRQ handler install/removeThomas Gleixner
2015-08-26MIPS: jz4740: Consolidate chained IRQ handler install/removeThomas Gleixner
2015-08-26MIPS: Set up FTLB probability for I6400Markos Chandras
2015-08-26MIPS: cpu-probe: Fix VTLB/FTLB configuration for R6Markos Chandras
2015-08-26MIPS: Add default case for the FTLB enable/disable codeMarkos Chandras
2015-08-26MIPS: cpu-probe: Remove cp0 hazard barrier when enabling the FTLBMarkos Chandras
2015-08-26MIPS: CM: Add support for reporting CM cache errorsMarkos Chandras
2015-08-26MIPS: CPC: Fix type for GCR CPC base reg for 64-bitMarkos Chandras
2015-08-26MIPS: CM: The CMGCRBase register is 64-bit on 64 bit kernels.Markos Chandras
2015-08-26MIPS: mips-cm: Extend CM accessors for 64-bit CPUsMarkos Chandras
2015-08-26MIPS: Add platform callback before initializing the L2 cacheMarkos Chandras
2015-08-26MIPS: CM3: Add support for CM3 L2 cache.Paul Burton
2015-08-26MIPS: CM: Add GCR_L2_CONFIG register accessorsPaul Burton
2015-08-26MIPS: mips-cm: Implement mips_cm_revisionPaul Burton
2015-08-26MIPS: Kconfig: Disable MIPS MT and SMP implementations for R6Markos Chandras
2015-08-26MIPS: Add MIPS I6400 probe supportMarkos Chandras
2015-08-26MIPS: Add cases for CPU_I6400Markos Chandras
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