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2024-12-30ARM: dts: imx6sl: add phy-3p0-supply to usb physStefan Kerkmann
The integrated usb phys are supplied by the 3p0 regulator, which has a voltage range of 2.625V to 3.4V. Thus the min and max values are corrected and the regulator added as a proper supply for the usb phys. This fixes the following warnings during the probe of the mxs_phy driver: mxs_phy 20c9000.usbphy: supply phy-3p0 not found, using dummy regulator mxs_phy 20ca000.usbphy: supply phy-3p0 not found, using dummy regulator The 3p0 regulator handling was introduced by commit 966d73152078 ("usb: phy: mxs: enable regulator phy-3p0 to improve signal qualilty")`. Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30ARM: dts: imx6qdl: add phy-3p0-supply to usb physStefan Kerkmann
The integrated usb phys are supplied by the 3p0 regulator, which has a voltage range of 2.625V to 3.4V. Thus the min and max values are corrected and the regulator added as a proper supply for the usb phys. This fixes the following warnings during the probe of the mxs_phy driver: mxs_phy 20c9000.usbphy: supply phy-3p0 not found, using dummy regulator mxs_phy 20ca000.usbphy: supply phy-3p0 not found, using dummy regulator The 3p0 regulator handling was introduced by commit 966d73152078 ("usb: phy: mxs: enable regulator phy-3p0 to improve signal qualilty")`. Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-29Merge tag 'x86-urgent-2024-12-29' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Ingo Molnar: - Fix a hang in the "kernel IBT no ENDBR" self-test that may trigger on FRED systems, caused by incomplete FRED state cleanup in the #CP fault handler - Improve TDX (Coco VM) guest unrecoverable error handling to not potentially leak decrypted memory * tag 'x86-urgent-2024-12-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: virt: tdx-guest: Just leak decrypted memory on unrecoverable errors x86/fred: Clear WFE in missing-ENDBRANCH #CPs
2024-12-29Merge tag 'perf-urgent-2024-12-29' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 perf fixes from Ingo Molnar: - Fix Intel Lunar Lake build-in event definitions - Fall back to (compatible) legacy features on new Intel PEBS format v6 hardware - Enable uncore support on Intel Clearwater Forest CPUs, which is the same as the existing Sierra Forest uncore driver * tag 'perf-urgent-2024-12-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86/intel: Fix bitmask of OCR and FRONTEND events for LNC perf/x86/intel/ds: Add PEBS format 6 perf/x86/intel/uncore: Add Clearwater Forest support
2024-12-29ARM: dts: samsung: exynos4212-tab3: Drop interrupt from WM1811 codecArtur Weber
This was initially copied from the Midas DTSI, but there is no proof that the same interrupt is also used on the Tab 3. The pin listed as the interrupt here is GPIO_HDMI_CEC on the Midas, but for the Tab 3 it is the headset button GPIO - GPIO_EAR_SEND_END. Drop the interrupt, since there is no proof that it is used. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20240816-midas-audio-tab3-v2-5-48ee7f2293b3@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29ARM: dts: samsung: exynos4212-tab3: Add MCLK2 clock to WM1811 codec configArtur Weber
In the schematics, the MCLK2 pin is shown as connected to CODEC_CLK32K, which is derived from the same 32KHZ_PMIC clock as Bluetooth/WiFi and GPS clocks. 32KHZ_PMIC is connected to the BTCLK pin, represented in mainline as S2MPS11_CLK_BT. Add the MCLK2 clock to the WM1811 codec clock property to properly describe the hardware. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20240816-midas-audio-tab3-v2-4-48ee7f2293b3@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29ARM: dts: samsung: exynos4212-tab3: Fix headset mic, add jack detectionArtur Weber
Set up headset mic bias regulator and add the necessary properties to the samsung,midas-audio node to allow for headset jack detection. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20240816-midas-audio-tab3-v2-3-48ee7f2293b3@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29ARM: dts: socfpga: remove non-existent DAC from CycloneV devkitConor Dooley
There is no Rohm DAC on the CycloneV devkit according to the online documentation for it that I could find, and it definitely does not have a dh2228fv as this device does not actually exist! Remove the DAC node from the devicetree as it is not acceptable to pretend to have a device on a board in order to bind the spidev driver in Linux. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240717-partake-antivirus-3347e415fb7d@spud Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29arm64: dts: exynos: gs101-oriole: add pd-disable and typec-power-opmodeAndré Draszik
When the serial console is enabled, we need to disable power delivery since serial uses the SBU1/2 pins and appears to confuse the TCPCI, resulting in endless interrupts. For now, change the DT such that the serial console continues working. Note1: We can not have both typec-power-opmode and new-source-frs-typec-current active at the same time, as otherwise DT binding checks complain. Note2: When using a downstream DT, the Pixel boot-loader will modify the DT accordingly before boot, but for this upstream DT it doesn't know where to find the TCPCI node. The intention is for this commit to be reverted once an updated Pixel boot-loader becomes available. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-5-1412783a6b01@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29arm64: dts: exynos: gs101-oriole: enable Maxim max77759 TCPCiAndré Draszik
On Pixel 6 (and Pro), a max77759 companion PMIC for USB Type-C applications is used, which contains four functional blocks (at distinct I2C addresses): * top (including GPIO) * charger * fuel gauge * TCPCi While in the same package, TCPCi and Fuel Gauge have separate I2C addresses, interrupt lines and interrupt status registers and can be treated independently. The TCPCi is required to detect and handle connector orientation in Pixel's USB PHY driver, and to configure the USB controller's role (host vs device). This change adds the TCPCi part as it can be independent and doesn't need a top-level MFD. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-4-1412783a6b01@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29x86/fred: Clear WFE in missing-ENDBRANCH #CPsXin Li (Intel)
An indirect branch instruction sets the CPU indirect branch tracker (IBT) into WAIT_FOR_ENDBRANCH (WFE) state and WFE stays asserted across the instruction boundary. When the decoder finds an inappropriate instruction while WFE is set ENDBR, the CPU raises a #CP fault. For the "kernel IBT no ENDBR" selftest where #CPs are deliberately triggered, the WFE state of the interrupted context needs to be cleared to let execution continue. Otherwise when the CPU resumes from the instruction that just caused the previous #CP, another missing-ENDBRANCH #CP is raised and the CPU enters a dead loop. This is not a problem with IDT because it doesn't preserve WFE and IRET doesn't set WFE. But FRED provides space on the entry stack (in an expanded CS area) to save and restore the WFE state, thus the WFE state is no longer clobbered, so software must clear it. Clear WFE to avoid dead looping in ibt_clear_fred_wfe() and the !ibt_fatal code path when execution is allowed to continue. Clobbering WFE in any other circumstance is a security-relevant bug. [ dhansen: changelog rewording ] Fixes: a5f6c2ace997 ("x86/shstk: Add user control-protection fault handler") Signed-off-by: Xin Li (Intel) <xin@zytor.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Acked-by: Dave Hansen <dave.hansen@linux.intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/all/20241113175934.3897541-1-xin%40zytor.com
2024-12-27Merge tag 'powerpc-6.13-3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc fix from Madhavan Srinivasan: - Add close() callback in vas_vm_ops struct for proper cleanup Thanks to Haren Myneni. * tag 'powerpc-6.13-3' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/pseries/vas: Add close() callback in vas_vm_ops struct
2024-12-27arm64: dts: qcom: x1e80100: Fix interconnect tags for SDHC nodesAbel Vesa
The CPU-to-SDHC interconnect path for the SDHC_2 needs to have the active-only tags. The tags are missing entirely on for the SDHC_4 controller interconnect paths. Fix all tags for both controllers. Fixes: ffb21c1e19b1 ("arm64: dts: qcom: x1e80100: Describe the SDHC controllers") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241227-b4-x1e80100-qcp-sdhc-fixes-v1-1-cd971f7f0955@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27riscv: defconfig: drop RT_GROUP_SCHED=yCeleste Liu
Commit ba6cfef057e1 ("riscv: enable Docker requirements in defconfig") introduced it because of Docker, but Docker has removed this requirement since [1] (2023-04-19). For cgroup v1, if turned on, and there's any cgroup in the "cpu" hierarchy it needs an RT budget assigned, otherwise the processes in it will not be able to get RT at all. The problem with RT group scheduling is that it requires the budget assigned but there's no way we could assign a default budget, since the values to assign are both upper and lower time limits, are absolute, and need to be sum up to < 1 for each individal cgroup. That means we cannot really come up with values that would work by default in the general case.[2] For cgroup v2, it's almost unusable as well. If it turned on, the cpu controller can only be enabled when all RT processes are in the root cgroup. But it will lose the benefits of cgroup v2 if all RT process were placed in the same cgroup. Red Hat, Gentoo, Arch Linux and Debian all disable it. systemd also doesn't support it.[3] [1]: https://github.com/moby/moby/commit/005150ed69c540fb0b5323e0f2208608c1204536 [2]: https://bugzilla.redhat.com/show_bug.cgi?id=1229700 [3]: https://github.com/systemd/systemd/issues/13781#issuecomment-549164383 Acked-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Celeste Liu <CoelacanthusHex@gmail.com> Acked-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20240910-fix-riscv-rt_group_sched-v3-1-486e75e5ae6d@gmail.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-12-26arm64: dts: qcom: qrb4210-rb2: add HDMI audio playback supportAlexey Klimov
Add sound node and dsp-related piece to enable HDMI audio playback support on Qualcomm QRB4210 RB2 board. That is the only sound output supported for now. The audio playback is verified using the following commands: amixer -c0 cset iface=MIXER,name='SEC_MI2S_RX Audio Mixer MultiMedia1' 1 aplay -D hw:0,0 /usr/share/sounds/alsa/Front_Center.wav Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241112025306.712122-5-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm4250: add LPASS LPI pin controllerAlexey Klimov
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node required for audio subsystem on Qualcomm QRB4210 RB2. QRB4210 is based on sm4250 which has a slightly different lpass pin controller comparing to sm6115. While at this, also add description of lpi_i2s2 pins (active state) required for audio playback via HDMI. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241112025306.712122-4-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm6115: add LPASS LPI pin controllerAlexey Klimov
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node required for audio subsystem on Qualcomm QRB4210 RB2. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241112025306.712122-3-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm6115: add apr and its servicesAlexey Klimov
Add apr (asynchronous packet router) node and its associated services required to enable audio on QRB4210 RB2 platform. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241112025306.712122-2-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8650: Fix CDSP context banks unit addressesKrzysztof Kozlowski
There is a mismatch between 'reg' property and unit address for last there CDSP compute context banks. Current values were taken as-is from downstream source. Considering that 'reg' is used by Linux driver as SID of context bank and that least significant bytes of IOMMU value match the 'reg', assume the unit-address is wrong and needs fixing. This also won't have any practical impact, except adhering to Devicetree spec. Fixes: dae8cdb0a9e1 ("arm64: dts: qcom: sm8650: Add three missing fastrpc-compute-cb nodes") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241104144204.114279-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26ARM: dts: qcom: sdx55: Add CPU PCIe EP interconnect pathKrishna chaitanya chundru
Add cpu-pcie interconnect path for PCIe EP to sdx55 platform. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1689751218-24492-4-git-send-email-quic_krichai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26ARM: dts: qcom: sdx65: Add PCIe EP interconnect pathKrishna chaitanya chundru
Add pcie-mem & cpu-pcie interconnect path ifor PCIe EP to sdx65 platform. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Link: https://lore.kernel.org/r/1689751218-24492-3-git-send-email-quic_krichai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: q[dr]u1000: move board clocks to qdu1000.dtsi fileDmitry Baryshkov
The QDU1000 and QRU1000 devices define XO and clocks completely in the board files, despite qdu1000.dtsi file referencing them directly. Follow the example of other platforms and move clock definitions to the qdu1000.dtsi file. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-21-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sdm670: move board clocks to sdm670.dtsi fileDmitry Baryshkov
The SDM670 devices define XO and clocks completely in the board files, despite sdm670.dtsi file referencing them directly. Follow the example of other platforms and move clock definitions to the sdm670.dtsi file. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-20-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sc8180x: drop extra XO clock frequenciesDmitry Baryshkov
sc8180x.dtsi already defines 38.4 MHz clock frequency for the XO clock. Drop duplicate overrides from Primus and Lenovo Flex 5G DT files. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-19-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: x1e80100: correct sleep clock frequencyDmitry Baryshkov
The X1E80100 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-18-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8650: correct sleep clock frequencyDmitry Baryshkov
The SM8650 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 6fbdb3c1fac7 ("arm64: dts: qcom: sm8650: add initial SM8650 MTP dts") Fixes: a834911d50c1 ("arm64: dts: qcom: sm8650: add initial SM8650 QRD dts") Fixes: 01061441029e ("arm64: dts: qcom: sm8650: add support for the SM8650-HDK board") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-17-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8550: correct sleep clock frequencyDmitry Baryshkov
The SM8550 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 0b12da4e28d8 ("arm64: dts: qcom: add base AIM300 dtsi") Fixes: b5e25ded2721 ("arm64: dts: qcom: sm8550: add support for the SM8550-HDK board") Fixes: 71342fb91eae ("arm64: dts: qcom: Add base SM8550 MTP dts") Fixes: d228efe88469 ("arm64: dts: qcom: sm8550-qrd: add QRD8550") Fixes: ba2c082a401f ("arm64: dts: qcom: sm8550: Add support for Samsung Galaxy Z Fold5") Fixes: 39c596304e44 ("arm64: dts: qcom: Add SM8550 Xperia 1 V") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-16-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8450: correct sleep clock frequencyDmitry Baryshkov
The SM8450 platform uses PMK8350 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-15-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8350: correct sleep clock frequencyDmitry Baryshkov
The SM8350 platform uses PMK8350 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-14-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8250: correct sleep clock frequencyDmitry Baryshkov
The SM8250 platform uses PM8150 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 9ff8b0591fcf ("arm64: dts: qcom: sm8250: use the right clock-freqency for sleep-clk") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-13-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm6375: correct sleep clock frequencyDmitry Baryshkov
The SM6375 platform uses PM6125 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 59d34ca97f91 ("arm64: dts: qcom: Add initial device tree for SM6375") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-12-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm6125: correct sleep clock frequencyDmitry Baryshkov
The SM6125 platform uses PM6125 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-11-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm4450: correct sleep clock frequencyDmitry Baryshkov
The SM4450 platform uses PM4450 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 7a1fd03e7410 ("arm64: dts: qcom: Adds base SM4450 DTSI") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-10-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sdx75: correct sleep clock frequencyDmitry Baryshkov
The SDX75 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 9181bb939984 ("arm64: dts: qcom: Add SDX75 platform and IDP board support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-9-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sc7280: correct sleep clock frequencyDmitry Baryshkov
The SC7280 platform uses PMK8350 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 7a1f4e7f740d ("arm64: dts: qcom: sc7280: Add basic dts/dtsi files for sc7280 soc") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-8-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sar2130p: correct sleep clock frequencyDmitry Baryshkov
The SAR2130P platform uses PM8150 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: be9115bfe5bf ("arm64: dts: qcom: sar2130p: add support for SAR2130P") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-7-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: qrb4210-rb2: correct sleep clock frequencyDmitry Baryshkov
Qualcomm RB2 board uses PM6125 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 8d58a8c0d930 ("arm64: dts: qcom: Add base qrb4210-rb2 board dts") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-6-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: q[dr]u1000: correct sleep clock frequencyDmitry Baryshkov
The Q[DR]U1000 platforms use PM8150 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: d1f2cfe2f669 ("arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-5-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: qcs404: correct sleep clock frequencyDmitry Baryshkov
The QCS40x platforms use PMS405 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 9181bb939984 ("arm64: dts: qcom: Add SDX75 platform and IDP board support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-4-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: msm8994: correct sleep clock frequencyDmitry Baryshkov
The MSM8994 platform uses PM8994/6 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: feeaf56ac78d ("arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-3-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: msm8939: correct sleep clock frequencyDmitry Baryshkov
The MSM8939 platform uses PM8916 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 61550c6c156c ("arm64: dts: qcom: Add msm8939 SoC") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-2-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: msm8916: correct sleep clock frequencyDmitry Baryshkov
The MSM8916 platform uses PM8916 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: f4fb6aeafaaa ("arm64: dts: qcom: msm8916: Add fixed rate on-board oscillators") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-1-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8650: correct MDSS interconnectsDmitry Baryshkov
SM8650 lists two interconnects for the display subsystem, mdp0-mem (between MDP and LLCC) and mdp1-mem (between LLCC and EBI, memory). The second interconnect is a misuse. mdpN-mem paths should be used for several outboud MDP interconnects rather than the path between LLCC and memory. This kind of misuse can result in bandwidth underflows, possibly degrading picture quality as the required memory bandwidth is divided between all mdpN-mem paths (and LLCC-EBI should not be a part of such division). Drop the second path and use direct MDP-EBI path for mdp0-mem until we support separate MDP-LLCC and LLCC-EBI paths. Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Cc: stable@kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241026-fix-sm8x50-mdp-icc-v2-2-fd8ddf755acc@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8550: correct MDSS interconnectsDmitry Baryshkov
SM8550 lists two interconnects for the display subsystem, mdp0-mem (between MDP and LLCC) and mdp1-mem (between LLCC and EBI, memory). The second interconnect is a misuse. mdpN-mem paths should be used for several outboud MDP interconnects rather than the path between LLCC and memory. This kind of misuse can result in bandwidth underflows, possibly degrading picture quality as the required memory bandwidth is divided between all mdpN-mem paths (and LLCC-EBI should not be a part of such division). Drop the second path and use direct MDP-EBI path for mdp0-mem until we support separate MDP-LLCC and LLCC-EBI paths. Fixes: d7da51db5b81 ("arm64: dts: qcom: sm8550: add display hardware devices") Cc: stable@kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241026-fix-sm8x50-mdp-icc-v2-1-fd8ddf755acc@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: qcs8300: Add LLCC support for QCS8300Jingyi Wang
Add Last Level Cache Controller node on the QCS8300 platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> Link: https://lore.kernel.org/r/20241031-qcs8300_llcc-v3-3-bb56952cb83b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: qcs8300: Add PMU support for QCS8300Jingyi Wang
Add Performance Monitoring Unit(PMU) nodes on the QCS8300 platform. Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241101-qcs8300_pmu-v1-1-3f3d744a3482@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8650: add interconnect and opp-peak-kBps for GPUNeil Armstrong
Each GPU OPP requires a specific peak DDR bandwidth, let's add those to each OPP and also the related interconnect path. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241217-topic-sm8x50-gpu-bw-vote-v6-7-1adaf97e7310@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8550: add interconnect and opp-peak-kBps for GPUNeil Armstrong
Each GPU OPP requires a specific peak DDR bandwidth, let's add those to each OPP and also the related interconnect path. Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241217-topic-sm8x50-gpu-bw-vote-v6-6-1adaf97e7310@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: qcs615-ride: Enable secondary USB controller on QCS615 RideKrishna Kurapati
Enable secondary USB controller on QCS615 Ride platform. The secondary USB controller is made "host", as it is a Type-A port. Secondary USB controller of QCS615 Ride has Type-A port exposed for connecting peripheral. The VBUS to the peripheral is provided by TPS2549IRTERQ1 regulator connected to the port. The regulator has an enable pin controlled by PM8150. Model it as fixed regulator and keep it Always-On at boot, since the regulator is GPIO controlled regulator. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Co-developed-by: Song Xue <quic_songxue@quicinc.com> Signed-off-by: Song Xue <quic_songxue@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241218-add_usb_host_mode_for_qcs615-v3-2-d9d29fe39a4b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: qcs615: Add support for secondary USB node on QCS615Krishna Kurapati
Add support for secondary USB controller and its high-speed phy on QCS615. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Co-developed-by: Song Xue <quic_songxue@quicinc.com> Signed-off-by: Song Xue <quic_songxue@quicinc.com> Link: https://lore.kernel.org/r/20241218-add_usb_host_mode_for_qcs615-v3-1-d9d29fe39a4b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-23 00:45:36 +0000