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2025-06-11ARM: dts: aspeed: Add device tree for Nvidia's GB200NVL BMCWillie Thai
The GB200NVL BMC is an Aspeed Ast2600 based BMC [1] for Nvidia Blackwell GB200NVL platform [2]. Co-developed-by: Mars Yang <maryang@nvidia.com> Signed-off-by: Mars Yang <maryang@nvidia.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: Paul Menzel <pmenzel@molgen.mpg.de> Cc: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://www.aspeedtech.com/server_ast2600/ [1] Link: https://nvdam.widen.net/s/wwnsxrhm2w/blackwell-datasheet-3384703 [2] Signed-off-by: Willie Thai <wthai@nvidia.com> Link: https://patch.msgid.link/20250401153955.314860-3-wthai@nvidia.com [arj: tidy commit message] Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: catalina: Enable MCTP support for NIC managementPotin Lai
Add the `mctp-controller` property and MCTP nodes to enable support for backend NIC management via PLDM over MCTP. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20250321-potin-catalina-dts-update-20250102-v6-10-4bd85efeb9b4@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: catalina: Update CBC FRU EEPROM I2C bus and addressPotin Lai
Revise the I2C bus and address for the Cable Backplane Cartridge (CBC) FRU EEPROM in the Catalina device tree. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20250321-potin-catalina-dts-update-20250102-v6-9-4bd85efeb9b4@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: catalina: Enable multi-master on additional I2C busesPotin Lai
Update the device tree to enable `multi-master` mode on I2C buses shared between the host BMC and the NV module with HMC. This ensures proper bus arbitration and coordination in multi-master environments, preventing communication conflicts and improving reliability. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20250321-potin-catalina-dts-update-20250102-v6-8-4bd85efeb9b4@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: catalina: Remove INA238 and INA230 nodesPotin Lai
Remove INA238 and INA230 power sensor nodes from the device tree (DTS) due to incompatibility with the second-source ISL28022, which shares the same I2C address. Move the driver probe to userspace to handle sensor dynamically. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20250321-potin-catalina-dts-update-20250102-v6-7-4bd85efeb9b4@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: catalina: Add second source HSC node supportPotin Lai
Add device tree nodes for the XDP710 Hot-Swap Controller (HSC) to support the Power Distribution Board (PDB) with a second-source configuration. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20250321-potin-catalina-dts-update-20250102-v6-6-4bd85efeb9b4@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: catalina: Add second source fan controller supportPotin Lai
Add device tree nodes for the NCT7363 fan controllers on the second-source Power Distribution Board (PDB). Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20250321-potin-catalina-dts-update-20250102-v6-5-4bd85efeb9b4@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: catalina: Add fan controller supportPotin Lai
Add device tree nodes for the MAX31790 fan controllers on the Power Distribution Board (PDB). These nodes enable fan speed control and monitoring, improving thermal management and system reliability. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20250321-potin-catalina-dts-update-20250102-v6-4-4bd85efeb9b4@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: catalina: Add MP5990 power sensor nodePotin Lai
Add a device tree node for the MP5990 power sensor to enable monitoring of the P12V supplying power to the fans. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20250321-potin-catalina-dts-update-20250102-v6-3-4bd85efeb9b4@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: catalina: Add Front IO board remote thermal sensorPotin Lai
Add a remote thermal sensor node for the Front IO board in the Catalina platform device tree. This sensor enables monitoring of the inlet temperature. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20250321-potin-catalina-dts-update-20250102-v6-2-4bd85efeb9b4@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: catalina: Add IO Mezz board thermal sensor nodesPotin Lai
Add thermal sensor nodes for the IO Mezzanine (IO Mezz) board in the Catalina platform device tree. These nodes enable temperature monitoring for the backend NIC, improving thermal management and monitoring capabilities. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20250321-potin-catalina-dts-update-20250102-v6-1-4bd85efeb9b4@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: system1: Disable gpio pull downNinad Palsule
Disable internal pull down for the following GPIO lines. - GPIOL4 - Reset PCH registers in the rtc. - GPIOL5 - Reset portition of Intel ME - GPIOL6 - FM smi active - GPIOL7 - psu all dc power good. Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Link: https://patch.msgid.link/20250204194115.3899174-10-ninad@linux.ibm.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: system1: Mark GPIO line high/lowNinad Palsule
- Mark following GPIO lines as input high: - GPIOL4 (reset PCH registers) - GPIOL5 (reset portition of intel ME) - Mark isolate errors from cpu1 gpio (GPIOO6) as active low output. - The fan controller reset line should be active high. Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Link: https://patch.msgid.link/20250204194115.3899174-9-ninad@linux.ibm.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: system1: Remove VRs max8952Ninad Palsule
Removing voltage regulators max8952 from device tree. Those are fully controlled by hardware and firmware should not touch them. Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Link: https://patch.msgid.link/20250204194115.3899174-8-ninad@linux.ibm.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: system1: Update LED gpio nameNinad Palsule
Rename LEDs with meaningful names for easier identification. Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Link: https://patch.msgid.link/20250204194115.3899174-7-ninad@linux.ibm.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: system1: Reduce sgpio speedNinad Palsule
Reduce sgpio speed to improve stability with the current PCB layout. Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Link: https://patch.msgid.link/20250204194115.3899174-6-ninad@linux.ibm.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: system1: Add GPIO line nameNinad Palsule
Add following GPIO line name so that userspace can control them - Flash write override - pch-reset Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Link: https://patch.msgid.link/20250204194115.3899174-5-ninad@linux.ibm.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: system1: Add IPMB deviceNinad Palsule
Add IPMB device sitting behind PCH module Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Link: https://patch.msgid.link/20250204194115.3899174-4-ninad@linux.ibm.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: bletchley: remove unused ethernet-phy nodePotin Lai
Remove the unused `ethernet-phy` node and the `phy-handle` property from the Bletchley device tree. This fixes warnings reported by the kernel DTB checks. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20250213-bletchley-dts-fix-v1-1-c953315eb894@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: Align GPIO hog name with bindingsKrzysztof Kozlowski
Bindings expect GPIO hog names to end with 'hog' suffix, so correct it to fix dtbs_check warnings like: aspeed-bmc-lenovo-hr630.dtb: pin_gpio_b5: $nodename:0: 'pin_gpio_b5' does not match '^.+-hog(-[0-9]+)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Ninad Palsule <ninad@linux.ibm.com> Link: https://patch.msgid.link/20250116090009.87338-1-krzysztof.kozlowski@linaro.org Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-11ARM: dts: aspeed: Remove swift machineJoel Stanley
This machine is no longer in use, and support was deleted from openbmc in March 2022. Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patch.msgid.link/20250115112239.430636-1-joel@jms.id.au Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-06-10arm64: dts: qcom: Add camera clock controller for sc8180xSatya Priya Kakitapalli
Add device node for camera clock controller on Qualcomm SC8180X platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-4-8fb1d3265f52@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10riscv: fix runtime constant support for nommu kernelsCharles Mirabile
the `__runtime_fixup_32` function does not handle the case where `val` is zero correctly (as might occur when patching a nommu kernel and referring to a physical address below the 4GiB boundary whose upper 32 bits are all zero) because nothing in the existing logic prevents the code from taking the `else` branch of both nop-checks and emitting two `nop` instructions. This leaves random garbage in the register that is supposed to receive the upper 32 bits of the pointer instead of zero that when combined with the value for the lower 32 bits yields an invalid pointer and causes a kernel panic when that pointer is eventually accessed. The author clearly considered the fact that if the `lui` is converted into a `nop` that the second instruction needs to be adjusted to become an `li` instead of an `addi`, hence introducing the `addi_insn_mask` variable, but didn't follow that logic through fully to the case where the `else` branch executes. To fix it just adjust the logic to ensure that the second `else` branch is not taken if the first instruction will be patched to a `nop`. Fixes: a44fb5722199 ("riscv: Add runtime constant support") Signed-off-by: Charles Mirabile <cmirabil@redhat.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20250530211422.784415-2-cmirabil@redhat.com Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2025-06-10riscv: vdso: Exclude .rodata from the PT_DYNAMIC segmentFangrui Song
.rodata is implicitly included in the PT_DYNAMIC segment due to inheriting the segment of the preceding .dynamic section (in both GNU ld and LLD). When the .rodata section's size is not a multiple of 16 bytes on riscv64, llvm-readelf will report a "PT_DYNAMIC dynamic table is invalid" warning. Note: in the presence of the .dynamic section, GNU readelf and llvm-readelf's -d option decodes the dynamic section using the section. This issue arose after commit 8f8c1ff879fab60f80f3a7aec3000f47e5b03ba9 ("riscv: vdso.lds.S: remove hardcoded 0x800 .text start addr"), which placed .rodata directly after .dynamic by removing .eh_frame. This patch resolves the implicit inclusion into PT_DYNAMIC by explicitly specifying the :text output section phdr. Reported-by: Nathan Chancellor <nathan@kernel.org> Closes: https://github.com/ClangBuiltLinux/linux/issues/2093 Signed-off-by: Fangrui Song <i@maskray.me> Tested-by: Nathan Chancellor <nathan@kernel.org> Link: https://lore.kernel.org/r/20250602-riscv-vdso-v1-1-0620cf63cff0@maskray.me Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2025-06-10arm64: dts: qcom: sm6350: Add video clock controllerLuca Weiss
Add a node for the videocc found on the SM6350 SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250324-sm6350-videocc-v2-4-cc22386433f4@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: qcs8300-ride: enable videoVikash Garodia
Enable video nodes on the qcs8300-ride board. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Vikash Garodia <quic_vgarodia@quicinc.com> Link: https://lore.kernel.org/r/20250501-qcs8300_iris-v7-5-b229d5347990@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: qcs8300: add video nodeVikash Garodia
Add the IRIS video-codec node on QCS8300 platform to support video functionality. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Vikash Garodia <quic_vgarodia@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250501-qcs8300_iris-v7-4-b229d5347990@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10x86/virt/tdx: Avoid indirect calls to TDX assembly functionsKai Huang
Two 'static inline' TDX helper functions (sc_retry() and sc_retry_prerr()) take function pointer arguments which refer to assembly functions. Normally, the compiler inlines the TDX helper, realizes that the function pointer targets are completely static -- thus can be resolved at compile time -- and generates direct call instructions. But, other times (like when CONFIG_CC_OPTIMIZE_FOR_SIZE=y), the compiler declines to inline the helpers and will instead generate indirect call instructions. Indirect calls to assembly functions require special annotation (for various Control Flow Integrity mechanisms). But TDX assembly functions lack the special annotations and can only be called directly. Annotate both the helpers as '__always_inline' to prod the compiler into maintaining the direct calls. There is no guarantee here, but Peter has volunteered to report the compiler bug if this assumption ever breaks[1]. Fixes: 1e66a7e27539 ("x86/virt/tdx: Handle SEAMCALL no entropy error in common code") Fixes: df01f5ae07dd ("x86/virt/tdx: Add SEAMCALL error printing for module initialization") Signed-off-by: Kai Huang <kai.huang@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/lkml/20250605145914.GW39944@noisy.programming.kicks-ass.net/ [1] Link: https://lore.kernel.org/all/20250606130737.30713-1-kai.huang%40intel.com
2025-06-10arm64: dts: qcom: sa8775p-ride: add anx7625 DSI to DP bridge nodesAyushi Makhija
Add anx7625 DSI to DP bridge device nodes. Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250604071851.1438612-3-quic_amakhija@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: sa8775p: add Display Serial Interface device nodesAyushi Makhija
Add device tree nodes for the DSI0 and DSI1 controllers with their corresponding PHYs found on Qualcomm SA8775P SoC. Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com> Reviewed-by: Dmitry Baryshkov <lumag@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250604071851.1438612-2-quic_amakhija@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: broadcom: northstar2: Drop GIC V2M "interrupt-parent"Rob Herring (Arm)
The default interrupt parent is a parent node containing "#interrupt-cells", so an explicit "interrupt-parent" is not necessary. Fixes these dtschema warnings: (arm,gic-400): v2m@70000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@60000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@50000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@40000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@30000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@20000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@10000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@0: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250609203705.2852500-1-robh@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-10arm64: dts: qcom: x1e80100: Add missing 'global' PCIe interruptManivannan Sadhasivam
'global' interrupt is used to receive PCIe controller and link specific events. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250227-pcie-global-irq-v1-23-2b70a7819d1e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: sar2130p: Add 'global' PCIe interruptManivannan Sadhasivam
'global' interrupt is used to receive PCIe controller and link specific events. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250227-pcie-global-irq-v1-22-2b70a7819d1e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: sc8180x: Add 'global' PCIe interruptManivannan Sadhasivam
'global' interrupt is used to receive PCIe controller and link specific events. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250227-pcie-global-irq-v1-21-2b70a7819d1e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: ipq6018: Add missing MSI and 'global' IRQsManivannan Sadhasivam
IPQ6018 has 8 MSI SPI interrupts and one 'global' interrupt. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250227-pcie-global-irq-v1-19-2b70a7819d1e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: ipq8074: Add missing MSI and 'global' IRQsManivannan Sadhasivam
IPQ8074 has 8 MSI SPI interrupts and one 'global' interrupt. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250227-pcie-global-irq-v1-17-2b70a7819d1e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: msm8998: Add missing MSI and 'global' IRQsManivannan Sadhasivam
MSM8998 has 8 MSI SPI interrupts and one 'global' interrupt. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250227-pcie-global-irq-v1-15-2b70a7819d1e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: msm8996: Add missing MSI SPI interruptsManivannan Sadhasivam
MSM8996 has 8 MSI SPI interrupts per controller instance. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250227-pcie-global-irq-v1-13-2b70a7819d1e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: sdm845: Add missing MSI and 'global' IRQsManivannan Sadhasivam
SDM845 has 8 MSI SPI interrupts and one 'global' interrupt per controller. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250227-pcie-global-irq-v1-12-2b70a7819d1e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: sc7280: Add 'global' PCIe interruptManivannan Sadhasivam
'global' interrupt is used to receive PCIe controller and link specific events. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250227-pcie-global-irq-v1-10-2b70a7819d1e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: sa8775p: Add 'global' PCIe interruptManivannan Sadhasivam
'global' interrupt is used to receive PCIe controller and link specific events. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250227-pcie-global-irq-v1-8-2b70a7819d1e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: sm8350: Add 'global' PCIe interruptManivannan Sadhasivam
'global' interrupt is used to receive PCIe controller and link specific events. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250227-pcie-global-irq-v1-6-2b70a7819d1e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: sm8250: Add 'global' PCIe interruptManivannan Sadhasivam
'global' interrupt is used to receive PCIe controller and link specific events. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250227-pcie-global-irq-v1-4-2b70a7819d1e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: sm8150: Add 'global' PCIe interruptManivannan Sadhasivam
'global' interrupt is used to receive PCIe controller and link specific events. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250227-pcie-global-irq-v1-2-2b70a7819d1e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10ARM: dts: qcom: Align wifi node name with bindingsKrzysztof Kozlowski
Since commit 3c3606793f7e ("dt-bindings: wireless: bcm4329-fmac: Use wireless-controller.yaml schema"), bindings expect 'wifi' as node name: qcom-msm8974-lge-nexus5-hammerhead.dtb: bcrmf@1: $nodename:0: 'bcrmf@1' does not match '^wifi(@.*)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250424084713.105080-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: x1e80100: describe uefi rtc offsetJohan Hovold
On many Qualcomm platforms the PMIC RTC control and time registers are read-only so that the RTC time can not be updated. Instead an offset needs be stored in some machine-specific non-volatile memory, which a driver can take into account. On platforms where the offset is stored in a Qualcomm specific UEFI variable the variables are also accessed in a non-standard way, which means that the OS cannot assume that the variable service is available by the time the RTC driver probes. Use the new 'qcom,uefi-rtc-info' property to indicate that the offset is stored in a UEFI variable so that the OS can determine whether to wait for it to become available. Fixes: b53c2c23d3c2 ("arm64: dts: qcom: x1e80100: enable rtc") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20250423075143.11157-5-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: qcom: sc8280xp-x13s: describe uefi rtc offsetJohan Hovold
On many Qualcomm platforms the PMIC RTC control and time registers are read-only so that the RTC time can not be updated. Instead an offset needs be stored in some machine-specific non-volatile memory, which a driver can take into account. On platforms where the offset is stored in a Qualcomm specific UEFI variable the variables are also accessed in a non-standard way, which means that the OS cannot assume that the variable service is available by the time the RTC driver probes. Use the new 'qcom,uefi-rtc-info' property to indicate that the offset is stored in a UEFI variable so that the OS can determine whether to wait for it to become available. Fixes: 409803681a55 ("arm64: dts: qcom: sc8280xp-x13s: switch to uefi rtc offset") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20250423075143.11157-4-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10arm64: dts: rockchip: convert rk3562 to their dt-binding constantsHeiko Stuebner
Now that the binding head has been merged, convert the power-domain ids back to these constants for easier handling. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250510161531.2086706-1-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-10arm64: dts: rockchip: Add Luckfox Omni3576 Board supportJohn Clark
Add device tree for the Luckfox Omni3576 Carrier Board with Core3576 Module, powered by the Rockchip RK3576 SoC with four Cortex-A72 cores, four Cortex-A53 cores, and a Mali-G52 MC3 GPU. This initial implementation enables essential functionality for booting Linux and basic connectivity. Supported and tested features: - UART for serial console - SD card for storage - PCIe with NVMe SSD (detected, mounted, and fully functional) - USB 2.0 host ports - RK806 PMIC for power management - RTC with timekeeping and wake-up - GPIO-controlled LED with heartbeat trigger - eMMC (enabled, not populated on tested board) The device tree provides a foundation for further peripheral support, such as WiFi, MIPI-DSI, HDMI, and Ethernet, in future updates. Tested on Linux 6.15-rc4 Based on the Luckfox SDK, which derives from Rockchip’s SDK examples, with relevant changes to align with upstream Linux. Signed-off-by: John Clark <inindev@gmail.com> Link: https://lore.kernel.org/r/20250516002713.145026-4-inindev@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-10arm64: dts: rockchip: Remove workaround that prevented Turing RK1 GPU power ↵Sam Edwards
regulator control The RK3588 GPU power domain cannot be activated unless the external power regulator is already on. When GPU support was added to this DT, we had no way to represent this requirement, so `regulator-always-on` was added to the `vdd_gpu_s0` regulator in order to ensure stability. A later patch series (see "Fixes:" commit) resolved this shortcoming, but that commit left the workaround -- and rendered the comment above it no longer correct. Remove the workaround to allow the GPU power regulator to power off, now that the DT includes the necessary information to power it back on correctly. Fixes: f94500eb7328b ("arm64: dts: rockchip: Add GPU power domain regulator dependency for RK3588") Signed-off-by: Sam Edwards <CFSworks@gmail.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20250608184855.130206-1-CFSworks@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit (git 2.34.1) at 2025-10-03 13:27:35 +0000