summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2025-04-23crypto: arm/sha1-neon - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also remove the unnecessary SIMD fallback path. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: arm/sha1-ce - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also remove the unnecessary SIMD fallback path. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: mips/octeon-sha1 - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: arm64/sha1 - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also remove the unnecessary SIMD fallback path. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: x86/sha1 - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also remove the unnecessary SIMD fallback path. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: sparc/md5 - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also switch to the generic export format. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: powerpc/md5 - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: mips/octeon-md5 - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also switch to the generic export format. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: x86/ghash - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also remove the unnecessary SIMD fallback path. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: s390/ghash - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also switch to the generic export format. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: riscv/ghash - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. As this was the last user relying on crypto/ghash.h for gf128mul.h, remove the unnecessary inclusion of gf128mul.h from crypto/ghash.h. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: arm64/ghash - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also remove the unnecessary SIMD fallback path. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: arm/ghash - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also switch to the generic export format. Finally remove a couple of stray may_use_simd() calls in gcm. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: powerpc/ghash - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: arm/blake2b - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also remove the unnecessary SIMD fallback path. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-22arm64: dts: add support for S7D based Amlogic BM202Xianwei Zhao
Amlogic S7D is an advanced application processor designed for hybrid OTT/IP Set Top Box and high-end media box applications. Add basic support for the S7D based Amlogic BM202 board, Reusing S7 basic components: CPU, GIC, IRQ, Timer and UART. These are capable of booting up into the serial console. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/r/20250317-s6-s7-basic-v1-7-d653384e41f3@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22arm64: dts: add support for S7 based Amlogic BP201Xianwei Zhao
Amlogic S7 is an advanced application processor designed for hybrid OTT/IP Set Top Box and high-end media box applications. Add basic support for the S7 based Amlogic BP201 board, which describes the following components: CPU, GIC, IRQ, Timer and UART. These are capable of booting up into the serial console. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/r/20250317-s6-s7-basic-v1-6-d653384e41f3@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22arm64: dts: add support for S6 based Amlogic BL209Xianwei Zhao
Amlogic S6 is an advanced application processor designed for hybrid OTT/IP Set Top Box and high-end media box applications. Add basic support for the S6 based Amlogic BL209 board, which describes the following components: CPU, GIC, IRQ, Timer and UART. These are capable of booting up into the serial console. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/r/20250317-s6-s7-basic-v1-5-d653384e41f3@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0Nícolas F. R. A. Prado
Add the firmware-name property for SCP core0 so the firmware can be loaded from its canonical location in the linux-firmware repository. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20250421-scp-dual-core-mt8390-v2-5-c84117a959a9@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-04-22arm64: dts: mediatek: mt8188: Describe SCP as a cluster with two coresNícolas F. R. A. Prado
The SCP is currently described in the Devicetree as a single-core processor, but really it is a cluster with two cores. Describe the full cluster but enable only core0 on the current mt8188 platforms since that's the only one usable with the upstream firmware. Co-developed-by: Tinghan Shen <tinghan.shen@mediatek.com> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Co-developed-by: Jason Chen <jason-ch.chen@mediatek.corp-partner.google.com> Signed-off-by: Jason Chen <jason-ch.chen@mediatek.corp-partner.google.com> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20250421-scp-dual-core-mt8390-v2-4-c84117a959a9@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-04-22x86/vdso: Remove redundant #ifdeffery around in_ia32_syscall()Thomas Weißschuh
The #ifdefs only guard code that is also guarded by in_ia32_syscall(), which already contains the same #ifdef itself. Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Andrew Cooper <andrew.cooper3@citrix.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Brian Gerst <brgerst@gmail.com> Cc: Eric Biederman <ebiederm@xmission.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Juergen Gross <jgross@suse.com> Cc: Kees Cook <kees@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@surriel.com> Link: https://lore.kernel.org/r/20240910-x86-vdso-ifdef-v1-2-877c9df9b081@linutronix.de
2025-04-22x86/vdso: Remove #ifdeffery around page setup variantsThomas Weißschuh
Replace the open-coded ifdefs in C sources files with IS_ENABLED(). This makes the code easier to read and enables the compiler to typecheck also the disabled parts, before optimizing them away. To make this work, also remove the ifdefs from declarations of used variables. Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Andrew Cooper <andrew.cooper3@citrix.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Brian Gerst <brgerst@gmail.com> Cc: Eric Biederman <ebiederm@xmission.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Juergen Gross <jgross@suse.com> Cc: Kees Cook <kees@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@surriel.com> Link: https://lore.kernel.org/r/20240910-x86-vdso-ifdef-v1-1-877c9df9b081@linutronix.de
2025-04-22arm64: dts: amlogic: S4: Add clk-measure controller nodeChuan Liu
Add the clk-measure controller node for S4 SoC family. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20250415-clk-measure-v3-7-9b8551dd33b4@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22arm64: dts: amlogic: C3: Add clk-measure controller nodeChuan Liu
Add the clk-measure controller node for C3 SoC family. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20250415-clk-measure-v3-6-9b8551dd33b4@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22arm64: dts: rockchip: Add rk3576 pcie nodesKever Yang
rk3576 has two pcie controllers, both are pcie2x1 work with naneng-combphy. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Shawn Lin <Shawn.lin@rock-chips.com> Reviewed-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250414145110.11275-3-kever.yang@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-22arm64: dts: rockchip: Enable HDMI audio outputs for Cool Pi CM5 EVBAndy Yan
Enable audio outputs for two HDMI ports on Cool Pi CM5 EVB Signed-off-by: Andy Yan <andyshrk@163.com> Link: https://lore.kernel.org/r/20250419121326.388298-3-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-22arm64: dts: rockchip: Enable HDMI1 on Cool Pi CM5 EVBAndy Yan
Enable the second HDMI output port on Cool Pi CM5 EVB Signed-off-by: Andy Yan <andyshrk@163.com> Link: https://lore.kernel.org/r/20250419121326.388298-2-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-22arm64: dts: rockchip: Rename hdmi-con to hdmi0-con for Cool Pi CM5 EVBAndy Yan
There are two hdmi connector on Cool Pi CM5 EVB, the current supported is hdmi0, assign corresponding index to it. It will be convenient for us to add support for another one. Signed-off-by: Andy Yan <andyshrk@163.com> Link: https://lore.kernel.org/r/20250419121326.388298-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-22arm64: dts: rockchip: Enable eDP0 display on RK3588S EVB1 boardDamon Ding
Add the necessary DT changes to enable eDP0 on RK3588S EVB1 board: - Set pinctrl of pwm12 for backlight - Enable edp0/hdptxphy0/vp2 - Assign the parent of DCLK_VOP2_SRC to PLL_V0PLL - Add aux-bus/panel nodes For RK3588, the PLL_V0PLL is specifically designed for the VOP2. This means the clock rate of PLL_V0PLL can be adjusted according to the dclk rate of relevant VP. It is typically assigned as the dclk source of a specific VP when the clock of relevant display mode is unusual, such as the eDP panel 'lg,lp079qx1-sp0v' paired with RK3588S EVB1, which has a clock rate of 202.02MHz. Additionally, the 'force-hpd' is set for edp0 because the HPD pin on the panel side is not connected to the eDP HPD pin on the SoC side according to the RK3588S EVB1 hardware design. Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Link: https://lore.kernel.org/r/20250310104114.2608063-14-damon.ding@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-22arm64: dts: rockchip: Add eDP0 node for RK3588Damon Ding
Add support for the eDP0 output on RK3588 SoC. Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Link: https://lore.kernel.org/r/20250310104114.2608063-13-damon.ding@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-04-22arm64: dts: renesas: rzg3e-smarc-som: Enable Mali-G52Tommaso Merciai
Enable the Mali-G52 (GPU) node on the RZ/G3E SMARC SoM board. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250402131142.1270701-5-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-22arm64: dts: renesas: r9a09g047: Add Mali-G52 GPU nodeTommaso Merciai
Add the Mali-G52 GPU node to the SoC DTSI. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250402131142.1270701-4-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-22arm64: dts: renesas: rzg3e-smarc-som: Add RAA215300 pmic supportJohn Madieu
Enable RAA215300 PMIC and built-in RTC support on the RZ/G3E SoM module. Also add related clock and interrupt signals. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250329121258.172099-3-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-22arm64: dts: renesas: rzg3e-smarc-som: Add I2C2 device pincontrolJohn Madieu
Add a device node for I2C2 pincontrol. Also enable the I2C2 device node with 1MHz clock frequency as it is connected to the RAA215300 PMIC on the RZ/G3E SoM. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250329121258.172099-2-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-22arm64: dts: exynos: Add DT node for all UART portsFaraz Ata
Universal Serial Interface (USI) supports three serial protocol like uart, i2c and spi. ExynosAutov920 has 18 instances of USI. Add all the USI DT node and subsequent uart nodes for all the instances. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Faraz Ata <faraz.ata@samsung.com> Link: https://lore.kernel.org/r/20250417113511.759268-1-faraz.ata@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-04-22arm64: dts: amlogic: Drop redundant CPU "clock-latency"Rob Herring (Arm)
The "clock-latency" property is part of the deprecated opp-v1 binding and is redundant if the opp-v2 table has equal or larger values in any "clock-latency-ns". Add any missing "clock-latency-ns" properties and remove "clock-latency". Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250410-dt-cpu-schema-v2-11-63d7dc9ddd0a@kernel.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22arm64: dts: amlogic: gxlx-s905l-p271: add saradc compatibleChristian Hewitt
Add the saradac node using the meson-gxlx-saradc compatible to ensure MPLL clocks are poked and audio output is enabled on the p271 (S905L) board. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20250330143254.3159519-1-christianshewitt@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22arm64: dts: amlogic: a1: enable UART RX and TX pull up by defaultMartin Blumenstingl
Some boards have noise on the UART RX line when the UART pins are not connected to another device (such as an USB UART adapter). This can be addressed by using a pull up resistor. Not all boards may provide such a pull up resistor on the PCB so enable the SoC's pull-up on the UART RX and TX pads by default. This matches the default (from u-boot or SoC hardware) state for the pinmux configuration on these pads. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250329185855.854186-8-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22arm64: dts: amlogic: axg: enable UART RX and TX pull up by defaultMartin Blumenstingl
Some boards have noise on the UART RX line when the UART pins are not connected to another device (such as an USB UART adapter). This can be addressed by using a pull up resistor. Not all boards may provide such a pull up resistor on the PCB so enable the SoC's pull-up on the UART RX and TX pads by default. This matches the default (from u-boot or SoC hardware) state for the pinmux configuration on these pads. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250329185855.854186-7-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22arm64: dts: amlogic: g12: enable UART RX and TX pull up by defaultMartin Blumenstingl
Some boards have noise on the UART RX line when the UART pins are not connected to another device (such as an USB UART adapter). This can be addressed by using a pull up resistor. Not all boards may provide such a pull up resistor on the PCB so enable the SoC's pull-up on the UART RX and TX pads by default. This matches the default (from u-boot or SoC hardware) state for the pinmux configuration on these pads. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250329185855.854186-6-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22arm64: dts: amlogic: gxl: enable UART RX and TX pull up by defaultMartin Blumenstingl
Some boards have noise on the UART RX line when the UART pins are not connected to another device (such as an USB UART adapter). This can be addressed by using a pull up resistor. Not all boards may provide such a pull up resistor on the PCB so enable the SoC's pull-up on the UART RX and TX pads by default. This matches the default (from u-boot or SoC hardware) state for the pinmux configuration on these pads. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250329185855.854186-5-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22arm64: dts: amlogic: gxbb: enable UART RX and TX pull up by defaultMartin Blumenstingl
Some boards have noise on the UART RX line when the UART pins are not connected to another device (such as an USB UART adapter). This can be addressed by using a pull up resistor. Not all boards may provide such a pull up resistor on the PCB so enable the SoC's pull-up on the UART RX and TX pads by default. This matches the default (from u-boot or SoC hardware) state for the pinmux configuration on these pads. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250329185855.854186-4-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22arm64: dts: amlogic: a4: add pinctrl nodeXianwei Zhao
Add pinctrl device to support Amlogic A4 and add uart pinconf. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250326-pinctrl-node-a4-v1-1-8c30639480f6@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22ARM: dts: amlogic: meson8b: enable UART RX and TX pull up by defaultMartin Blumenstingl
Some boards have noise on the UART RX line when the UART pins are not connected to another device (such as an USB UART adapter). This can be addressed by using a pull up resistor. Not all boards may provide such a pull up resistor on the PCB so enable the SoC's pull-up on the UART RX and TX pads by default. This matches the default (from u-boot or SoC hardware) state for the pinmux configuration on these pads. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250329185855.854186-3-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22ARM: dts: amlogic: meson8: enable UART RX and TX pull up by defaultMartin Blumenstingl
Some boards have noise on the UART RX line when the UART pins are not connected to another device (such as an USB UART adapter). This can be addressed by using a pull up resistor. Not all boards may provide such a pull up resistor on the PCB so enable the SoC's pull-up on the UART RX and TX pads by default. This matches the default (from u-boot or SoC hardware) state for the pinmux configuration on these pads. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250329185855.854186-2-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22x86/asm: Retire RIP_REL_REF()Ard Biesheuvel
Now that all users have been moved into startup/ where PIC codegen is used, RIP_REL_REF() is no longer needed. Remove it. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Brian Gerst <brgerst@gmail.com> Cc: David Woodhouse <dwmw@amazon.co.uk> Cc: Dionna Amalie Glaze <dionnaglaze@google.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Juergen Gross <jgross@suse.com> Cc: Kees Cook <keescook@chromium.org> Cc: Kevin Loughlin <kevinloughlin@google.com> Cc: Len Brown <len.brown@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lore.kernel.org/r/20250418141253.2601348-14-ardb+git@google.com
2025-04-22x86/boot: Drop RIP_REL_REF() uses from early SEV codeArd Biesheuvel
Now that the early SEV code is built with -fPIC, RIP_REL_REF() has no effect and can be dropped. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Brian Gerst <brgerst@gmail.com> Cc: David Woodhouse <dwmw@amazon.co.uk> Cc: Dionna Amalie Glaze <dionnaglaze@google.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Juergen Gross <jgross@suse.com> Cc: Kees Cook <keescook@chromium.org> Cc: Kevin Loughlin <kevinloughlin@google.com> Cc: Len Brown <len.brown@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lore.kernel.org/r/20250418141253.2601348-13-ardb+git@google.com
2025-04-22x86/boot: Move SEV startup code into startup/Ard Biesheuvel
Move the SEV startup code into arch/x86/boot/startup/, where it will reside along with other code that executes extremely early, and therefore needs to be built in a special manner. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Brian Gerst <brgerst@gmail.com> Cc: David Woodhouse <dwmw@amazon.co.uk> Cc: Dionna Amalie Glaze <dionnaglaze@google.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Juergen Gross <jgross@suse.com> Cc: Kees Cook <keescook@chromium.org> Cc: Kevin Loughlin <kevinloughlin@google.com> Cc: Len Brown <len.brown@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lore.kernel.org/r/20250418141253.2601348-12-ardb+git@google.com
2025-04-22x86/sev: Split off startup code from core codeArd Biesheuvel
Disentangle the SEV core code and the SEV code that is called during early boot. The latter piece will be moved into startup/ in a subsequent patch. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Brian Gerst <brgerst@gmail.com> Cc: David Woodhouse <dwmw@amazon.co.uk> Cc: Dionna Amalie Glaze <dionnaglaze@google.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Juergen Gross <jgross@suse.com> Cc: Kees Cook <keescook@chromium.org> Cc: Kevin Loughlin <kevinloughlin@google.com> Cc: Len Brown <len.brown@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lore.kernel.org/r/20250418141253.2601348-11-ardb+git@google.com
2025-04-22x86/sev: Move noinstr NMI handling code into separate source fileArd Biesheuvel
GCC may ignore the __no_sanitize_address function attribute when inlining, resulting in KASAN instrumentation in code tagged as 'noinstr'. Move the SEV NMI handling code, which is noinstr, into a separate source file so KASAN can be disabled on the whole file without losing coverage of other SEV core code, once the startup code is split off from it too. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Brian Gerst <brgerst@gmail.com> Cc: David Woodhouse <dwmw@amazon.co.uk> Cc: Dionna Amalie Glaze <dionnaglaze@google.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Juergen Gross <jgross@suse.com> Cc: Kees Cook <keescook@chromium.org> Cc: Kevin Loughlin <kevinloughlin@google.com> Cc: Len Brown <len.brown@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lore.kernel.org/r/20250418141253.2601348-10-ardb+git@google.com
generated by cgit (git 2.34.1) at 2025-09-30 19:08:57 +0000