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2025-04-16arm64: dts: mediatek: mt7622: Align GPIO hog name with bindingsKrzysztof Kozlowski
Bindings expect GPIO hog names to end with 'hog' suffix, so correct it to fix dtbs_check warning: mt7622-bananapi-bpi-r64.dtb: asm_sel: $nodename:0: 'asm_sel' does not match '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$' Link: https://lore.kernel.org/r/20250115211801.194247-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-04-16crypto: x86/poly1305 - don't select CRYPTO_LIB_POLY1305_GENERICEric Biggers
The x86 Poly1305 code never falls back to the generic code, so selecting CRYPTO_LIB_POLY1305_GENERIC is unnecessary. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16crypto: x86/poly1305 - remove redundant shash algorithmEric Biggers
Since crypto/poly1305.c now registers a poly1305-$(ARCH) shash algorithm that uses the architecture's Poly1305 library functions, individual architectures no longer need to do the same. Therefore, remove the redundant shash algorithm from the arch-specific code and leave just the library functions there. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16crypto: mips/poly1305 - remove redundant shash algorithmEric Biggers
Since crypto/poly1305.c now registers a poly1305-$(ARCH) shash algorithm that uses the architecture's Poly1305 library functions, individual architectures no longer need to do the same. Therefore, remove the redundant shash algorithm from the arch-specific code and leave just the library functions there. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16crypto: mips/poly1305 - drop redundant dependency on CONFIG_MIPSEric Biggers
arch/mips/crypto/Kconfig is sourced only when CONFIG_MIPS is enabled, so there is no need for options defined in that file to depend on it. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16crypto: arm64/poly1305 - remove redundant shash algorithmEric Biggers
Since crypto/poly1305.c now registers a poly1305-$(ARCH) shash algorithm that uses the architecture's Poly1305 library functions, individual architectures no longer need to do the same. Therefore, remove the redundant shash algorithm from the arch-specific code and leave just the library functions there. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16crypto: arm/poly1305 - remove redundant shash algorithmEric Biggers
Since crypto/poly1305.c now registers a poly1305-$(ARCH) shash algorithm that uses the architecture's Poly1305 library functions, individual architectures no longer need to do the same. Therefore, remove the redundant shash algorithm from the arch-specific code and leave just the library functions there. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16crypto: poly1305 - centralize the shash wrappers for arch codeEric Biggers
Following the example of the crc32, crc32c, and chacha code, make the crypto subsystem register both generic and architecture-optimized poly1305 shash algorithms, both implemented on top of the appropriate library functions. This eliminates the need for every architecture to implement the same shash glue code. Note that the poly1305 shash requires that the key be prepended to the data, which differs from the library functions where the key is simply a parameter to poly1305_init(). Previously this was handled at a fairly low level, polluting the library code with shash-specific code. Reorganize things so that the shash code handles this quirk itself. Also, to register the architecture-optimized shashes only when architecture-optimized code is actually being used, add a function poly1305_is_arch_optimized() and make each arch implement it. Change each architecture's Poly1305 module_init function to arch_initcall so that the CPU feature detection is guaranteed to run before poly1305_is_arch_optimized() gets called by crypto/poly1305.c. (In cases where poly1305_is_arch_optimized() just returns true unconditionally, using arch_initcall is not strictly needed, but it's still good to be consistent across architectures.) Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16crypto: powerpc/poly1305 - implement library instead of shashEric Biggers
Currently the Power10 optimized Poly1305 is only wired up to the crypto_shash API, which makes it unavailable to users of the library API. The crypto_shash API for Poly1305 is going to change to be implemented on top of the library API, so the library API needs to be supported. And of course it's needed anyway to serve the library users. Therefore, change the Power10 optimized Poly1305 code to implement the library API instead of the crypto_shash API. Cc: Danny Tsen <dtsen@linux.ibm.com> Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16crypto: cbcmac - Set block size properlyHerbert Xu
The block size of a hash algorithm is meant to be the number of bytes its block function can handle. For cbcmac that should be the block size of the underlying block cipher instead of one. Set the block size of all cbcmac implementations accordingly. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16crypto: lib/sm3 - Move sm3 library into lib/cryptoHerbert Xu
Move the sm3 library code into lib/crypto. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16crypto: arm64/sha512 - Fix header inclusionsHerbert Xu
Instead of relying on linux/module.h being included through the header file sha512_base.h, include it directly. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16x86: Make simd.h more resilientHerbert Xu
Add missing header inclusions and protect against double inclusion. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16arm: Make simd.h more resilientHerbert Xu
Add missing header inclusions and protect against double inclusion. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16crypto: powerpc - Include uaccess.h and othersHerbert Xu
The powerpc aes/ghash code was relying on pagefault_disable from being pulled in by random header files. Fix this by explicitly including uaccess.h. Also add other missing header files to prevent similar problems in future. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16arm64: dts: exynos: update all samsung,mode constantsIvaylo Ivanov
Update all samsung,mode property values to account for renaming USI_V2 constants to USI_MODE in the bindings. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20250209132043.3906127-1-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-04-16Merge branch 'x86/cpu' into x86/fpu, to pick up dependent commitsIngo Molnar
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2025-04-16watchdog: diag288_wdt: Implement module autoloadHeiko Carstens
The s390 specific diag288_wdt watchdog driver makes use of the virtual watchdog timer, which is available in most machine configurations. If executing the diagnose instruction with subcode 0x288 results in an exception the watchdog timer is not available, otherwise it is available. In order to allow module autoload of the diag288_wdt module, move the detection of the virtual watchdog timer to early boot code, and provide its availability as a cpu feature. This allows to make use of module_cpu_feature_match() to automatically load the module iff the virtual watchdog timer is available. Suggested-by: Marc Hartmayer <mhartmay@linux.ibm.com> Tested-by: Mete Durlu <meted@linux.ibm.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20250410095036.1525057-1-hca@linux.ibm.com Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
2025-04-16x86/cpu: Add CPU model number for Bartlett Lake CPUs with Raptor Cove coresPi Xiange
Bartlett Lake has a P-core only product with Raptor Cove. [ mingo: Switch around the define as pointed out by Christian Ludloff: Ratpr Cove is the core, Bartlett Lake is the product. Signed-off-by: Pi Xiange <xiange.pi@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Christian Ludloff <ludloff@gmail.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Tony Luck <tony.luck@intel.com> Cc: Andrew Cooper <andrew.cooper3@citrix.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: John Ogness <john.ogness@linutronix.de> Cc: "Ahmed S. Darwish" <darwi@linutronix.de> Cc: x86-cpuid@lists.linux.dev Link: https://lore.kernel.org/r/20250414032839.5368-1-xiange.pi@intel.com
2025-04-16Merge branch 'linus' into x86/cpu, to resolve conflictsIngo Molnar
Conflicts: tools/arch/x86/include/asm/cpufeatures.h Signed-off-by: Ingo Molnar <mingo@kernel.org>
2025-04-15arm64: dts: qcom: sm8750-qrd: Enable modemKrzysztof Kozlowski
Enable the modem (MPSS) on QRD8750 board. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250221-b4-sm8750-modem-v3-3-462dae7303c7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sm8750-mtp: Enable modemKrzysztof Kozlowski
Enable the modem (MPSS) on MPT8750 board. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250221-b4-sm8750-modem-v3-2-462dae7303c7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sm8750: Add Modem / MPSSKrzysztof Kozlowski
Add nodes for the MPSS and its SMP2P. These are compatible with earlier SM8650 with difference in lack of fifth memory region for Qlink Logging. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250221-b4-sm8750-modem-v3-1-462dae7303c7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: qcs6490-rb3gen2: Update the LPASS audio nodeTaniya Das
Update the lpassaudio node to support the new compatible as the lpassaudio needs to support the reset functionality on the QCS6490 RB3Gen2 board and the rest of the Audio functionality would be provided from the LPASS firmware. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250221-lpass_qcm6490_resets-v5-4-6be0c0949a83@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: qcm6490-idp: Update the LPASS audio nodeTaniya Das
Update the lpassaudio node to support the new compatible as the lpassaudio needs to support the reset functionality on the QCM6490 IDP board and the rest of the Audio functionality would be provided from the LPASS firmware. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250221-lpass_qcm6490_resets-v5-3-6be0c0949a83@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sa8775p: Remove cdsp compute-cb@10Karthik Sanagavarapu
Remove the context bank compute-cb@10 because these SMMU ids are S2-only which is not used for S1 transaction. Fixes: f7b01bfb4b47 ("arm64: qcom: sa8775p: Add ADSP and CDSP0 fastrpc nodes") Cc: stable@kernel.org Signed-off-by: Karthik Sanagavarapu <quic_kartsana@quicinc.com> Signed-off-by: Ling Xu <quic_lxu5@quicinc.com> Link: https://lore.kernel.org/r/4c9de858fda7848b77ea8c528c9b9d53600ad21a.1739260973.git.quic_lxu5@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sa8775p: Remove extra entries from the iommus propertyLing Xu
There are some items come out to be same value if we do SID & ~MASK. Remove extra entries from the iommus property for sa8775p to simplify. Fixes: f7b01bfb4b47 ("arm64: qcom: sa8775p: Add ADSP and CDSP0 fastrpc nodes") Cc: stable@kernel.org Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Ling Xu <quic_lxu5@quicinc.com> Link: https://lore.kernel.org/r/49f463415c8fa2b08fbc2317e31493362056f403.1739260973.git.quic_lxu5@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: defconfig: Enable IPQ5424 RDP466 base configsSricharan Ramabadhran
Enable GCC, Pinctrl for Qualcomm's IPQ5424 SoC which is required to boot IPQ5424-RDP466 boards to a console shell. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Link: https://lore.kernel.org/r/20241028060506.246606-7-quic_srichara@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sm8650: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-20-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sm8550: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-19-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sm8450: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-18-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sm8350: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-17-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sm8250: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-16-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sm8150: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-15-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sm6350: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-14-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sm6125: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-13-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sm6115: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-12-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sdm845: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-11-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sdm670: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-10-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sc8280xp: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-9-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sc8180x: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-8-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sc7280: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-7-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sc7180: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-6-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sa8775p: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-5-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: qcm2290: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-4-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: msm8998: use correct size for VBIF regionsDmitry Baryshkov
Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-3-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sa8775p: mark MDP interconnects as ALWAYS onDmitry Baryshkov
Change the tag for MDP interconnects to QCOM_ICC_TAG_ALWAYS, so that if CPUSS collapses, the display may stay on. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-2-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sc7280: Use the header with DSI phy clock IDsDmitry Baryshkov
Use the header with DSI phy clock IDs to make code more readable. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-1-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15arm64: dts: qcom: sdm660-xiaomi-lavender: Add missing SD card detect GPIOAlexey Minnekhanov
During initial porting these cd-gpios were missed. Having card detect is beneficial because driver does not need to do polling every second and it can just use IRQ. SD card detection in U-Boot is also fixed by this. Fixes: cf85e9aee210 ("arm64: dts: qcom: sdm660-xiaomi-lavender: Add eMMC and SD") Signed-off-by: Alexey Minnekhanov <alexeymin@postmarketos.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415130101.1429281-1-alexeymin@postmarketos.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-15x86/cpufeatures: Shorten X86_FEATURE_AMD_HETEROGENEOUS_CORESXin Li (Intel)
Shorten X86_FEATURE_AMD_HETEROGENEOUS_CORES to X86_FEATURE_AMD_HTR_CORES to make the last column aligned consistently in the whole file. No functional changes. Suggested-by: Borislav Petkov (AMD) <bp@alien8.de> Signed-off-by: Xin Li (Intel) <xin@zytor.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/20250415175410.2944032-4-xin@zytor.com
generated by cgit (git 2.34.1) at 2025-10-02 02:56:32 +0000