| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-11-22 | soc: sifive: ccache: Add StarFive JH7100 support | Emil Renner Berthing | |
| This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> | |||
| 2023-11-22 | soc: sifive: shunt ccache driver to drivers/cache | Conor Dooley | |
| Move the ccache driver over to drivers/cache, out of the drivers/soc dumping ground, to this new collection point for cache controller drivers. Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> | |||
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index : linux-arm.git | |
| Russell King's ARM Linux kernel tree | Russell King |
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