summaryrefslogtreecommitdiff
path: root/drivers/clk/at91/sama7g5.c
AgeCommit message (Expand)Author
2021-10-26clk: at91: sama7g5: set low limit for mck0 at 32KHzClaudiu Beznea
2021-10-26clk: at91: sama7g5: remove prescaler part of master clockClaudiu Beznea
2021-10-26clk: at91: clk-master: add notifier for dividerClaudiu Beznea
2021-10-26clk: at91: clk-sam9x60-pll: add notifier for div part of PLLClaudiu Beznea
2021-10-26clk: at91: sama7g5: add securam's peripheral clockClaudiu Beznea
2021-08-28clk: at91: sama7g5: remove all kernel-doc & kernel-doc warningsRandy Dunlap
2021-03-13clk: at91: Trivial typo fixes in the file sama7g5.cBhaskar Chowdhury
2020-12-19clk: at91: sama7g5: register cpu clockClaudiu Beznea
2020-12-19clk: at91: clk-master: re-factor master clockClaudiu Beznea
2020-12-19clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHzClaudiu Beznea
2020-12-19clk: at91: sama7g5: decrease lower limit for MCK0 rateClaudiu Beznea
2020-12-19clk: at91: sama7g5: remove mck0 from parent list of other clocksClaudiu Beznea
2020-12-19clk: at91: clk-sam9x60-pll: allow runtime changes for pllClaudiu Beznea
2020-12-19clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristicsEugen Hristev
2020-12-19clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DTEugen Hristev
2020-12-19dt-bindings: clock: at91: add sama7g5 pll definesEugen Hristev
2020-12-19clk: at91: sama7g5: fix compilation errorClaudiu Beznea
2020-07-24clk: at91: sama7g5: add clock support for sama7g5Claudiu Beznea