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path: root/drivers/clk/axs10x
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2017-07-17clk: axs10x: introduce AXS10X pll driverEugeniy Paltsev
AXS10X boards manages it's clocks using various PLLs. These PLL has same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the following devices: * ARC core on AXC CPU tiles. * ARC PGU on ARC SDP Mainboard. and more to come later. By this patch we add support for two plls (arc core pll and pgu pll), so we had to use two different init types: CLK_OF_DECLARE for arc core pll and regular probing for pgu pll. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Signed-off-by: Jose Abreu <joabreu@synopsys.com> [sboyd@codeaurora.org: Silence dubious !x & y sparse warning, make of_axs10x_pll_clk_setup() unregister clk on failure] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk/axs10x: Clear init field in driver probeJose Abreu
Init field must be cleared in driver probe as this structure is not dinamically allocated. If not, wrong flags can be passed to core. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: Carlos Palminha <palminha@synopsys.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Fixes: 923587aafc2c ("clk/axs10x: Add I2S PLL clock driver") Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/040cc9afdfa0e95ce7a01c406ff427ef7dc0c0fd.1481540717.git.joabreu@synopsys.com
2016-05-06clk/axs10x: Add I2S PLL clock driverJose Abreu
The ARC SDP I2S clock can be programmed using a specific PLL. This patch has the goal of adding a clock driver that programs this PLL. At this moment the rate values are hardcoded in a table but in the future it would be ideal to use a function which determines the PLL values given the desired rate. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>