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path: root/drivers/clk/keystone
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2016-12-08clk: keystone: pll: Unmap region obtained by of_iomapArvind Yadav
Free memory mapping, if of_pll_div_clk_init is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: keystone: improve function-level documentationJulia Lawall
Adjust the documentation to use the actual function names. Issue detected using Coccinelle (http://coccinelle.lip6.fr/) Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-19clk: keystone: fix a trivial typoGeliang Tang
s/regsiter/register/ Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd
* cleanup-clk-h-includes: (62 commits) clk: Remove clk.h from clk-provider.h clk: h8300: Remove clk.h and clkdev.h includes clk: at91: Include clk.h and slab.h clk: ti: Switch clk-provider.h include to clk.h clk: pistachio: Include clk.h clk: ingenic: Include clk.h clk: si570: Include clk.h clk: moxart: Include clk.h clk: cdce925: Include clk.h clk: Include clk.h in clk.c clk: zynq: Include clk.h clk: ti: Include clk.h clk: sunxi: Include clk.h and remove unused clkdev.h includes clk: st: Include clk.h clk: qcom: Include clk.h clk: highbank: Include clk.h clk: bcm: Include clk.h clk: versatile: Remove clk.h and clkdev.h includes clk: ux500: Remove clk.h and clkdev.h includes clk: tegra: Properly include clk.h ...
2015-07-28clk: keystone: make use of of_clk_parent_fill helper functionDinh Nguyen
Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20clk: keystone: Remove clk.h includeStephen Boyd
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Remove the include here because this is a provider driver. Cc: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-18clk: keystone: add support for post divider register for main pllMurali Karicheri
Main PLL controller has post divider bits in a separate register in pll controller. Use the value from this register instead of fixed divider when available. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2014-02-10clk: keystone: gate: fix clk_init_data initializationIvan Khoronzhuk
The clk_init_data struct is allocated in the stack. All members of this struct should be initialized before using otherwise it will lead to unpredictable situation as it can contain garbage. Ultimately the clk->flag field contains garbage. In my case it leads that flag CLK_IGNORE_UNUSED is set for most of clocks. As result a bunch of unused clocks cannot be disabled. So initialize flags in this structure too. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-12-10clk: keystone: gate: fix error handling on initGrygorii Strashko
This patch fixes Keystone gate control clock driver initialization path: 1) clk_register_psc() returns error code and not a pure pointer, hence its return value need to be checked using IS_ERR(clk) macro. 2) Mapped IO memory isn't unmapped in case of errors, hence fix it. Cc: Mike Turquette <mturquette@linaro.org Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-12-10clk: keystone: use clkod register bits for postdivMurali Karicheri
DDR3A/B, ARM and PA PLL controllers have clkod register bits for configuring postdiv values. So use it instead of using fixed post dividers for these pll controllers. Assume that if fixed-postdiv attribute is not present, use clkod register value for pistdiv. Also update the Documentation of bindings to reflect the same. Cc: Mike Turquette <mturquette@linaro.org Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-10-07clk: keystone: Build Keystone clock driversSantosh Shilimkar
Now build the keystone common clock drivers. The build is made conditional based on COMMON_CLK_KEYSTONE Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-10-07clk: keystone: Add gate control clock driverSantosh Shilimkar
Add the driver for the clock gate control which uses PSC (Power Sleep Controller) IP on Keystone 2 based SOCs. It is responsible for enabling and disabling of the clocks for different IPs present in the SoC. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-10-07clk: keystone: add Keystone PLL clock driverSantosh Shilimkar
Add the driver for the PLL IPs found on Keystone 2 devices. The PLL IP typically has a multiplier, a divider and a post-divider. The PLL IPs like ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where as the Main PLL is controlled by a PLL controller and memory map registers. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>