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path: root/drivers/clk/meson/axg.c
AgeCommit message (Expand)Author
2019-02-04clk: meson: factorise meson64 peripheral clock controller driversJerome Brunet
2019-02-02clk: meson: rework and clean drivers dependenciesJerome Brunet
2019-01-18clk: meson: axg: claim clock controller input clock from DTJerome Brunet
2018-11-08clk: meson: axg: mark fdiv2 and fdiv3 as criticalJerome Brunet
2018-09-26clk: meson-axg: pcie: drop the mpll3 clock parentYixun Lan
2018-09-26clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet
2018-09-26clk: meson: clk-pll: remove od parametersJerome Brunet
2018-09-26clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet
2018-09-26clk: meson: clk-pll: add enable bitJerome Brunet
2018-07-09clk: meson: add gen_clkJerome Brunet
2018-07-09clk: meson-axg: add clocks required by pcie driverYixun Lan
2018-07-09clk: meson: remove obsolete register accessJerome Brunet
2018-05-21clk: meson: axg: let mpll clocks round closestJerome Brunet
2018-03-14clk: meson: Drop unused local variable and add staticStephen Boyd
2018-03-13clk: meson: add fdiv clock gatesJerome Brunet
2018-03-13clk: meson: add mpll pre-dividerJerome Brunet
2018-03-13clk: meson: axg: add hifi pll clockJerome Brunet
2018-03-13clk: meson: add gp0 frac parameter for axg and gxlJerome Brunet
2018-03-13clk: meson: remove special gp0 lock loopJerome Brunet
2018-03-13clk: meson: poke pll CNTL lastJerome Brunet
2018-03-13clk: meson: use hhi syscon if availableJerome Brunet
2018-03-13clk: meson: split divider and gate part of mpllJerome Brunet
2018-03-13clk: meson: migrate plls clocks to clk_regmapJerome Brunet
2018-03-13clk: meson: migrate mplls clocks to clk_regmapJerome Brunet
2018-03-13clk: meson: migrate muxes to clk_regmapJerome Brunet
2018-03-13clk: meson: migrate dividers to clk_regmapJerome Brunet
2018-03-13clk: meson: migrate gates to clk_regmapJerome Brunet
2018-03-13clk: meson: add regmap to the clock controllersJerome Brunet
2018-03-13clk: meson: remove obsolete commentsJerome Brunet
2018-03-13clk: meson: only one loop index is necessary in probeJerome Brunet
2018-03-13clk: meson: use devm_of_clk_add_hw_providerJerome Brunet
2018-03-13clk: meson: use dev pointer where possibleJerome Brunet
2018-02-12clk: meson: add axg misc bit to the mpll driverJerome Brunet
2018-02-12clk: meson: axg: fix the od shift of the sys_pllYixun Lan
2018-02-12clk: meson: axg: add the fractional part of the fixed_pllJerome Brunet
2018-02-12clk: meson: remove useless pll rate params tablesJerome Brunet
2018-01-10clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()weiyongjun (A)
2017-12-28clk: meson-axg: make local symbol axg_gp0_params_table staticweiyongjun (A)
2017-12-28clk: meson-axg: fix return value check in axg_clkc_probe()weiyongjun (A)
2017-12-14clk: meson-axg: add clock controller driversQiufang Dai