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path: root/drivers/clk/mstar
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2021-02-16clk: mstar: msc313-mpll: Fix format specifierDaniel Palmer
The output dividers are unsigned int so the format specifier should have been %u not %d. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Link: https://lore.kernel.org/r/20210215115710.3762276-2-daniel@0x0f.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-16clk: mstar: Allow MStar clk drivers to be compile testedDaniel Palmer
Allow COMPILE_TEST to also build the MStar clk drivers instead of only building them when ARCH_MSTARV7 is selected. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Suggested-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210215115710.3762276-1-daniel@0x0f.com [sboyd@kernel.org: Drop regmap select too] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: mstar: MStar/SigmaStar MPLL driverDaniel Palmer
This adds a basic driver for the MPLL block found in MStar/SigmaStar ARMv7 SoCs. Currently this driver is only good for calculating the rates of it's outputs and the actual configuration must be done before the kernel boots. Usually this is done even before u-boot starts. This driver targets the MPLL block found in the MSC313/MSC313E but there is no documentation this chip so the register descriptions for the another MStar chip the MST786 were used as they seem to match. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Link: https://lore.kernel.org/r/20210211052206.2955988-5-daniel@0x0f.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>