summaryrefslogtreecommitdiff
path: root/drivers/clk/renesas/rzg2l-cpg.h
AgeCommit message (Expand)Author
2021-12-08clk: renesas: r9a07g044: Add mux and divider for G clockBiju Das
2021-11-19clk: renesas: rzg2l: Add CPG_PL1_DDIV macroBiju Das
2021-11-15clk: renesas: rzg2l: Add missing kerneldoc for resetsGeert Uytterhoeven
2021-10-08clk: renesas: r9a07g044: Add SDHI clock and reset entriesBiju Das
2021-10-08clk: renesas: rzg2l: Add SDHI clk mux supportBiju Das
2021-10-08clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...Lad Prabhakar
2021-09-24clk: renesas: rzg2l: Add support to handle coupled clocksBiju Das
2021-09-24clk: renesas: r9a07g044: Add ethernet clock sourcesBiju Das
2021-09-24clk: renesas: rzg2l: Add support to handle MUX clocksBiju Das
2021-07-19clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]Geert Uytterhoeven