Age | Commit message (Expand) | Author |
---|---|---|
2021-12-08 | clk: renesas: r9a07g044: Add mux and divider for G clock | Biju Das |
2021-11-19 | clk: renesas: rzg2l: Add CPG_PL1_DDIV macro | Biju Das |
2021-11-15 | clk: renesas: rzg2l: Add missing kerneldoc for resets | Geert Uytterhoeven |
2021-10-08 | clk: renesas: r9a07g044: Add SDHI clock and reset entries | Biju Das |
2021-10-08 | clk: renesas: rzg2l: Add SDHI clk mux support | Biju Das |
2021-10-08 | clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co... | Lad Prabhakar |
2021-09-24 | clk: renesas: rzg2l: Add support to handle coupled clocks | Biju Das |
2021-09-24 | clk: renesas: r9a07g044: Add ethernet clock sources | Biju Das |
2021-09-24 | clk: renesas: rzg2l: Add support to handle MUX clocks | Biju Das |
2021-07-19 | clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch] | Geert Uytterhoeven |