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path:
root
/
drivers
/
clk
/
rockchip
/
clk-rk3568.c
Age
Commit message (
Expand
)
Author
2024-05-04
clk: rockchip: rk3568: Add PLL rate for 724 MHz
Lucas Stach
2024-04-10
clk: rockchip: rk3568: Add missing USB480M_PHY mux
David Jander
2024-01-25
clk: rockchip: rk3568: Add PLL rate for 128MHz
Chris Morgan
2024-01-12
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
2023-12-05
clk: rockchip: rk3568: Mark pclk_usb as critical
Chris Morgan
2023-12-05
clk: rockchip: rk3568: Add PLL rate for 126.4MHz
Chris Morgan
2023-11-16
clk: rockchip: rk3568: Add PLL rate for 292.5MHz
Chris Morgan
2023-11-16
clk: rockchip: rk3568: Add PLL rate for 115.2MHz
Chris Morgan
2023-08-30
Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...
Stephen Boyd
2023-07-19
clk: Explicitly include correct DT includes
Rob Herring
2023-07-10
clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
Alibek Omarov
2023-07-10
clk: rockchip: rk3568: Add PLL rate for 101MHz
Alibek Omarov
2022-05-03
clk: rockchip: Mark hclk_vo as critical on rk3568
Sascha Hauer
2022-02-23
clk/rockchip: Use of_device_get_match_data()
Minghao Chi (CGEL ZTE)
2022-02-08
clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568
Sascha Hauer
2022-02-08
clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568
Sascha Hauer
2022-02-08
clk: rockchip: Add more PLL rates for rk3568
Sascha Hauer
2021-11-02
clk: rockchip: drop module parts from rk3399 and rk3568 drivers
Heiko Stuebner
2021-11-02
Revert "clk: rockchip: use module_platform_driver_probe"
Heiko Stuebner
2021-09-21
clk: rockchip: use module_platform_driver_probe
Miles Chen
2021-05-24
clk: rockchip: fix rk3568 cpll clk gate bits
Peter Geis
2021-03-21
clk: rockchip: add clock controller for rk3568
Elaine Zhang