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path: root/drivers/clk/rockchip
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2017-08-23clk: rockchip: Mark rockchip_fractional_approximation staticStephen Boyd
Silence the sparse warning clk/rockchip/clk.c:172:6: warning: symbol 'rockchip_fractional_approximation' was not declared. Should it be static? Cc: Elaine Zhang <zhangqing@rock-chips.com> Cc: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-22clk: rockchip: fix the rv1108 clk_mac sel register descriptionElaine Zhang
The source clock ordering is wrong, as shown in the TRM: cru_sel24_con[8] rmii_extclk_sel clock source select control register 1'b0: from internal PLL 1'b1: from external IO Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-22clk: rockchip: rename rv1108 macphy clock to macElaine Zhang
This MAC has no internal phy for rv1108 and the whole clock infrastructure hasn't been used yet, so is safe to fix. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-22clk: rockchip: add rv1108 ACLK_GMAC and PCLK_GMAC clocksElaine Zhang
Add gmac aclk and pclk clock gates. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-22clk: rockchip: add rk3228 SCLK_SDIO_SRC clk idElaine Zhang
In some special circumstances, may be need to reparent clk for sclk_sdio_src. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-08clk: rockchip: add special approximation to fix up fractional clk's jitterElaine Zhang
>From Rockchips fractional divider description: 3.1.9 Fractional divider usage To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by fractional divider. Generally you must set that denominator is 20 times larger than numerator to generate precise clock frequency. So the fractional divider applies only to generate low frequency clock like I2S, UART. Therefore add a special approximation function that handles this special requirement. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-08clk: rockchip: modify rk3128 clk driver to also support rk3126Elaine Zhang
rk3128 and rk3126 have some gate registers describe differences. So need to make some distinctions. The RK3126 and RK3128 Same clock description we move it to the common clock branches. And the different clks description use the own clock branches. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-08clk: rockchip: add some critical clocks for rv1108 SoCElaine Zhang
the bus/periph/nclk_ddrupctl/pclk_ddrmon/pclk_acodecphy/pclk_pmu no driver to handle them, Chip design requirements for these clock to always on. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-08clk: rockchip: rename some of clks for rv1108 SoCElaine Zhang
Rename some of clks to keep the consistency with the TRM. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-08clk: rockchip: fix up some clks describe error for rv1108 SoCElaine Zhang
1. fix up the parent name 2. remove the CLK_IGNORE_UNUSED flag for some clk not need to always on. 3. fix up some clks regs describe error. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-08clk: rockchip: support more clks for rv1108Elaine Zhang
Add the description of the missing clock, make the clock more complete. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-08clk: rockchip: fix up the pll clks error for rv1108 SoCElaine Zhang
fix up the lock_shift describe error. remove the ROCKCHIP_PLL_SYNC_RATE flag for gpll. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-06clk: rockchip: support more rates for rv1108 cpuclkElaine Zhang
fix up the cpuclk rates table for support more freqs. fix up the mux_core_mask describe error. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02clk: rockchip: mark some special clk as critical on rk3368Elaine Zhang
The jtag clk no driver to handle them. But this clk need enable,so make it as critical. The ddrphy/ddrupctl clks no driver to handle them, Chip design requirements for these clock to always on, The pmu_hclk_otg0 is Chip design defect, must be always on, Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02clk: rockchip: mark noc and some special clk as critical on rk3288Elaine Zhang
The atclk/dbg/jtag/hsic-xin12m/pclk_core clks no driver to handle them. But this clks need enable,so make it as ignore_unused for now. The ddrupctl0/ddrupctl1/publ0/publ1 clks no driver to handle them, Chip design requirements for these clock to always on, The pmu_hclk_otg0 is Chip design defect, must be always on, Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02clk: rockchip: mark noc and some special clk as critical on rk3228Elaine Zhang
The jtag/bus/peri/initmem/rom/stimer/phy clks no driver to handle them. But this clks need enable,so make it as critical. The ddrupctl/ddrmon/ddrphy clks no driver to handle them, Chip design requirements for these clock to always on, The hclk_otg_pmu is Chip design defect, must be always on, The new document will update the description of this clock. All these non-noc/non-arbi clocks,IC suggest always on, Because it's have some order limitation, between the NOC clock switch and bus IDLE(or pd on/off). The software is not very good to solve this constraint. Always on these clocks, has no effect on the system power consumption. The new document will update the description of these clock. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036Elaine Zhang
No driver to handle this clk yet, but chip design requiress for this clock supplying the ddr controller to be always on. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02clk: rockchip: add clock controller for rk3128Elaine Zhang
Add the clock tree definition for the new rk3128 SoC. And it also applies to the RK3126 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02clk: rockchip: export more rk3228 clocks idsElaine Zhang
This patch exports related BUS/VPU/RGA/HDCP/IEP/TSP/WIFI/ VIO/USB/EFUSE/GPU/CRYPTO clocks for dts reference. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02clk: rockchip: add ids for rk3399 testclks used for camera handlingEddie Cai
clk_testout1 and clk_testout2 are used for camera handling, so add their ids. Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-05-17clk: rockchip: fix up the RK3228 clk cpu setting tableElaine Zhang
support more cpu freq, and add armcore div setting. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-04-12Merge tag 'v4.12-rockchip-clk1' of ↵Michael Turquette
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: General rockchip clock changes for 4.12. Contains some new clock-ids as well as fixups of the clock-ids on rk3368 timers, which were unused and completely wrong (more and differently named timers). Also there is one new clock on rk3328 using the muxgrf type, a fix for pll enablement which should wait for the pll to lock before continuing, some more critical clocks and the rename of the rk1108 to rv1108, as the soc seems to have been using a preliminary name before its actual release. The plan is to have the driver changes (pinctrl, clk) go through the respective maintainer trees and once everything landed in mainline do the rename of the devicetree files. With the dts-include change in the clock rename, we also keep everything compiling and thus bisectability. * tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: add pll_wait_lock for pll_enable clk: rockchip: rename RK1108 to RV1108 dt-bindings: rk1108-cru: rename RK1108 to RV1108 clk: rockchip: mark some rk3368 core-clks as critical clk: rockchip: export SCLK_TIMERXX id for timers on rk3368 clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328 clk: rockchip: add clock ids for timer10-15 of RK3368 SoCs clk: rockchip: fix up rk3368 timer-ids clk: rockchip: add rk3328 clk_mac2io_ext ID clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399
2017-03-22clk: rockchip: add pll_wait_lock for pll_enableElaine Zhang
If pll is power down,when power up pll need wait pll lock. The reference documents section: PLL frequency change and lock check Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-03-22clk: rockchip: rename RK1108 to RV1108Andy Yan
Rockchip finally named the SOC as RV1108, so change it. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> [include rename in rk1108.dtsi to prevent compile errors] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-03-10clk: rockchip: mark some rk3368 core-clks as criticalElaine Zhang
Mark pclk_pd_alive, pclk_peri, hclk_peri as critical Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-03-10clk: rockchip: export SCLK_TIMERXX id for timers on rk3368Elaine Zhang
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-03-10clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328Elaine Zhang
With the newly introduced clk type for muxes in the grf we now can describe some missing clocks, like the clk_gmac2io and clk_gmac2phy that selects between clk_mac2io_src and gmac_clkin based on a bit set in the general register files. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-03-07clk: rockchip: Make uartpll a child of the gpll on rk3036Heiko Stuebner
The shared uart-pll is on boot a child of the apll that can get changed by cpu frequency scaling. So move it away to the more stable gpll to make sure the uart doesn't break on cpu frequency changes. This turned up during the 4.11 merge-window when commit 6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used") added general termios enablement making the uart on rk3036 change frequency and thus making it susceptible for the frequency scaling issue. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-03-07clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036Heiko Stuebner
The mux_pll_src_apll_dpll_gpll_usb480m_p parent list was missing a "," between the 3rd and 4th parent names, making them fall together and thus lookups fail. Fix that. Fixes: 5190c08b2989 ("clk: rockchip: add clock controller for rk3036") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-03-06clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399Douglas Anderson
The PMU Cortex M0 on rk3399 is intended to be used for things like DDRFreq transitions, suspend/resume, and other things that are the purview of ARM Trusted Firmware and not the kernel. As such, the kernel shouldn't be messing with the clocks. Add CLK_IGNORE_UNUSED to these clocks. Without this change, the following was observed on a Chromebook with a rk3399 (using not-yet-upstream ARM Trusted Firmware code and not-yet-upstream kernel code based on kernel-4.4): 1. We init the clock framework. 2. We start up "DDRFreq", which causes ATF to occasionally fire up the M0 for transitions. Each time ATF fires up the M0 it will turn on these clocks and each time it is done it will turn them off. 3. We finally get to the the part of the kernel that calls clk_disable_unused() and we disables the clocks. You can see the race above. Basically everything is fine as long as ARM Trusted Firmware isn't starting up the M0 at exactly the same time that the kernel is disabling unused clocks. ...but if the race happens then we go boom. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-23clk: rockchip: rk3288: make all niu clocks criticalJacob Chen
NIU clocks are related to the interconnect and it's important to other blocks. Since we don't have a driver to handle it, we should always enable it to avoid casually close. Make all of them critical,so that we don't have to each clock on its own once things break. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> [dropped the matching CLK_IGNORE_UNUSED flags] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-22clk: rockchip: use rk3288 vip_out clock idsJacob Chen
Reference the newly added vip clock-ids in the clock-tree. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-18clk: rockchip: fix the incorrect pclk_edp div width for RK3399Xing Zheng
The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5. Reported-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Tested-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-13clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188Heiko Stuebner
Add the newly added clock ids to the clock entries of the rk3066/rk3188 clock driver. We won't be needing them in the kernel for a bit yet but as they're used in the new u-boot ddr setup code/dts we should make sure the clock ids stay identical and do not differ. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-13clk: rockchip: use rk3288 isp_in clock idsJacob Chen
Reference the newly added isp clock-ids in the clock-tree. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-06clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFERDouglas Anderson
When we used to defer setting the "grf" member to rockchip_clk_get_grf() it was important to init the "grf" member to an error value in rockchip_clk_init(). With recent changes, we now set "grf" right in rockchip_clk_init() (two lines below the place where we initted it). That makes the old init useless. Get rid of it. Fixes: 6f339dc2719e ("clk: rockchip: lookup General Register Files in rockchip_clk_init") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-05clk: rockchip: add clock controller for rk3328Elaine Zhang
Add the clock tree definition for the new rk3328 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-02clk: rockchip: add new pll-type for rk3328Elaine Zhang
The rk3328's pll and clock are similar with rk3036's, it different with pll_mode_mask, the rk3328 soc pll mode only one bit(rk3036 soc have two bits) so these should be independent and separate from the series of rk3328s. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-02clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288Heiko Stuebner
With the newly introduced clk type for muxes in the grf we now can describe some missing clocks, like the aclk_vcodec that selects between aclk_vdpu and aclk_vepu based on a bit set in the general register files. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-02clk: rockchip: add a clock-type for muxes based in the grfHeiko Stuebner
Rockchip socs often have some tiny number of muxes not controlled from the core clock controller but through bits set in the general register files. Add a clock-type that can control these as well, so that we don't need to work around them being absent. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-12-06Merge tag 'v4.10-rockchip-clk2' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: A new clock controller for the rk1108 soc (single-core Cortex-A7+DSP), a fix making sure the cpuclk rate is actually valid, before trying to set it and a copy-paste fix for the rk3399's testclk. * tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: add clock controller for rk1108 dt-bindings: add documentation for rk1108 cru clk: rockchip: add dt-binding header for rk1108 clk: rockchip: fix copy-paste error in rk3399 testclk clk: rockchip: validity should be checked prior to cpu clock rate change
2016-11-16clk: rockchip: add clock controller for rk1108Shawn Lin
Add the clock tree definition and driver for rk1108 SoC. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: Jacob Chen <jacob2.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-16clk: rockchip: fix copy-paste error in rk3399 testclkJianqun Xu
Fix RK3368_* to RK3399_* for rk3399 clk_test clock. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-14Merge tag 'v4.10-rockchip-clk1' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk driver updates from Heiko Stuebner: PLL initialization for PLLs having both an integral and fractional mode (rk3036, rk3399) does now take into account the mode that the PLL is actually running at. As always also some additional and optimized PLL rates for rk3066 and rk3399, some additional clock ids for rk3066 and some additional clocks on rk3399 are now sucessfully handled inside their respective driver. * tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree clk: rockchip: add 400MHz to rk3066 clock rates table clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399 clk: rockchip: Use clock ids for cpu and peri clocks on rk3066 clk: rockchip: Add binding ids for cpu and peri clocks on rk3066 clk: rockchip: add 533.25MHz to rk3399 clock rates table
2016-11-14clk: rockchip: validity should be checked prior to cpu clock rate changeElaine Zhang
If validity is not checked prior to clock rate change, clk_set_rate( cpu_clk, unsupported_rate) will return success, but the real clock rate change operation is prohibited in post clock change event. Alough post clock change event will report error due to unsupported clock rate is set, but this error message is ignored by clock framework. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Tested-by: Rocky Hao <rocky.hao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-05clk: rockchip: Ignore frac divisor for PLL equivalence when it's unusedJulius Werner
Rockchip RK3399 PLLs can be used in two separate modes: integral and fractional. We can select between these two modes with the unambiguously named DSMPD bit. During boot, we check all PLL settings to confirm that they match our PLL table for that frequency, and reinitialize the PLLs where they don't. The settings checked for this include the fractional divider field that is only used in fractional mode, even if we're in integral mode (DSMPD = 1) and that field has no effect. This patch changes the check to only compare the fractional divider if we're actually in fractional mode. This way, we won't reinitialize the PLL in cases where there's absolutely no reason for that, which may avoid glitching child clocks that should better not be glitched (e.g. PWM regulators). Signed-off-by: Julius Werner <jwerner@chromium.org> [cloned the fix to the pretty similar rk3036 pll] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-05clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktreeJianqun Xu
Optimize rk3399 clocktree by removing CLK_IGNORE_UNUSED of some clocks. clocks will managered by usb: - clk_usbphy0_480m_src - clk_usbphy1_480m_src - clk_usbphy_480m clocks will be managered by pvtm: - clk_pvtm_core_l - clk_pvtm_core_b - clk_pvtm_ddr clocks will be managered by dfi: - pclk_ddr_mon - clk_dfimon0_timer - clk_dfimon1_timer - aclk_dcf - pclk_dcf Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-05clk: rockchip: add 400MHz to rk3066 clock rates tablePaweł Jarosz
We need this to init PLL_CPLL to 400MHz at boot. Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-02clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399Xing Zheng
Usually, the 800MHz and 1GHz are supplied for CPLL and NPLL in the RK3399. But dues to the carelessly copying from RK3036 when the RK3399 bringing up, the refdiv == 6, it will increase the lock time, and it is not an optimal configuration. Let's fix them for the lock time and jitter are lower: 800 MHz: - FVCO == 2.4 GHz, revdiv == 1. 1 GHz: - FVCO == 3 GHz, revdiv == 1. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-10-21clk: rockchip: Use clock ids for cpu and peri clocks on rk3066Paweł Jarosz
Add bindings for ACLK_CPU, HCLK_CPU, PCLK_CPU, ACLK_PERI, HCLK_PERI, PCLK_PERI. We need this to init it's rate at boot time. Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit (git 2.34.1) at 2024-06-09 01:54:55 +0000