| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-01-11 | clk: socfpga: stratix10: fix rate calculation for pll clocks | Dinh Nguyen | |
| The main PLL calculation has a mistake. We should be using the multiplying the VCO frequency, not the parent clock frequency. Fixes: 07afb8db7340 ("clk: socfpga: stratix10: add clock driver for Stratix10 platform") Cc: linux-stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> | |||
| 2018-04-06 | clk: socfpga: stratix10: add clock driver for Stratix10 platform | Dinh Nguyen | |
| Add a clock driver for the Stratix10 SoC. The driver is similar to the Cyclone5/Arria10 platforms, with the exception that this driver only uses one single clock binding. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> | |||
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index : linux-arm.git | |
| Russell King's ARM Linux kernel tree | Russell King |
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