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path: root/drivers/clk/sunxi-ng
AgeCommit message (Expand)Author
2017-09-13Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2017-08-31Merge tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kern...Stephen Boyd
2017-08-30clk: sunxi-ng: Provide a default reset hookMaxime Ripard
2017-08-30clk: sunxi-ng: a83t: Support new timing mode for mmc2 clockChen-Yu Tsai
2017-08-30clk: sunxi-ng: Add MP_MMC clocks that support MMC timing modes switchingChen-Yu Tsai
2017-08-30clk: sunxi-ng: Add interface to query or configure MMC timing modes.Chen-Yu Tsai
2017-08-24clk: sunxi-ng: Add sun4i/sun7i CCU driverPriit Laes
2017-08-23Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kern...Stephen Boyd
2017-08-19clk: sunxi-ng: support R40 SoCIcenowy Zheng
2017-08-14clk: sunxi-ng: nkm: add support for fixed post-dividerIcenowy Zheng
2017-08-14clk: sunxi-ng: div: Add support for fixed post-dividerPriit Laes
2017-08-04clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3Icenowy Zheng
2017-08-04clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate changeChen-Yu Tsai
2017-08-02Merge branch 'clk-fixes' into clk-nextStephen Boyd
2017-08-01clk: sunxi-ng: Wait for lock when using fractional modeJernej Škrabec
2017-08-01clk: sunxi-ng: Make fractional helper less chattyJernej Škrabec
2017-08-01clk: sunxi-ng: multiplier: Fix fractional modeJernej Škrabec
2017-08-01clk: sunxi-ng: Fix fractional mode for N-M clocksJernej Škrabec
2017-07-27clk: sunxi-ng: Fix header guard of ccu-sun8i-r.hMatthias Kaehlcke
2017-07-24clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clockMaxime Ripard
2017-07-21clk: Convert to using %pOF instead of full_nameRob Herring
2017-06-16clk: sunxi-ng: Staticize ccu_mux_helper_unapply_prediv()Stephen Boyd
2017-06-16Merge tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel...Stephen Boyd
2017-06-14Merge tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/...Stephen Boyd
2017-06-07clk: sunxi-ng: Move all clock types to a libraryStephen Boyd
2017-06-07clk: sunxi-ng: a83t: Add support for A83T's PRCMChen-Yu Tsai
2017-06-07clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83tArnd Bergmann
2017-06-07clk: sunxi-ng: a83t: Fix audio PLL divider offsetChen-Yu Tsai
2017-06-07clk: sunxi-ng: a83t: Fix PLL lock status register offsetChen-Yu Tsai
2017-06-07clk: sunxi-ng: Add driver for A83T CCUChen-Yu Tsai
2017-06-07clk: sunxi-ng: Support multiple variable pre-dividersChen-Yu Tsai
2017-06-07clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR()Wei Yongjun
2017-06-07clk: sunxi-ng: sun5i: Export video PLLsMaxime Ripard
2017-06-07clk: sunxi-ng: mux: Re-adjust parent rateMaxime Ripard
2017-06-07clk: sunxi-ng: mux: Change pre-divider application function prototypeMaxime Ripard
2017-06-07clk: sunxi-ng: mux: split out the pre-divider computation codeMaxime Ripard
2017-06-07clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENTMaxime Ripard
2017-06-07clk: sunxi-ng: div: Switch to divider_round_rateMaxime Ripard
2017-06-07clk: sunxi-ng: Pass the parent and a pointer to the clocks round rateMaxime Ripard
2017-06-07clk: sunxi-ng: explicitly include linux/spinlock.hTobias Klauser
2017-06-07clk: sunxi-ng: add support for DE2 CCUIcenowy Zheng
2017-05-31clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCMChen-Yu Tsai
2017-05-31clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCMChen-Yu Tsai
2017-05-25clk: sunxi-ng: sun5i: Fix ahb_bist_clk definitionBoris Brezillon
2017-05-18clk: sunxi-ng: enable SUNXI_CCU_MP for PRCMArnd Bergmann
2017-05-14clk: sunxi-ng: v3s: Fix usb otg device reset bitYong Deng
2017-05-14clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offsetChen-Yu Tsai
2017-05-10Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2017-04-28clk: sunxi-ng: always select CCU_GATEArnd Bergmann
2017-04-21Merge tag 'sunxi-clk-for-4.12-2' of https://git.kernel.org/pub/scm/linux/kern...Stephen Boyd
generated by cgit (git 2.34.1) at 2025-03-25 23:37:47 +0000