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path: root/drivers/clk/tegra/clk-divider.c
AgeCommit message (Expand)Author
2020-01-10clk: tegra: divider: Check UART's divider enable-bit state on rate's recalcul...Dmitry Osipenko
2019-11-11clk: tegra: divider: Save and restore divider rateSowjanya Komatineni
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner
2019-04-25clk: tegra: divider: Mark Memory Controller clock as read-onlyDmitry Osipenko
2018-08-14Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter',...Stephen Boyd
2018-07-25clk: tegra: Refactor fractional divider calculationPeter De Schrijver
2018-07-08clk: tegra: Mark Memory Controller clock as criticalDmitry Osipenko
2015-11-16tegra/clk-divider: fix wrong do_div() usageNicolas Pitre
2015-07-20clk: tegra: Properly include clk.hStephen Boyd
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding
2014-02-17clk: tegra: use max divider if divider overflowsAndrew Bresticker
2013-01-28clk: tegra: add Tegra specific clocksPrashant Gaikwad