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path: root/drivers/clk/tegra/clk-tegra210.c
AgeCommit message (Expand)Author
2017-11-01clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()Nicolin Chen
2017-10-19clk: tegra: Fix sor1_out clock implementationThierry Reding
2017-08-23clk: tegra: Fix Tegra210 PLLU initializationAlex Frid
2017-08-23clk: tegra: Correct Tegra210 UTMIPLL poweron delayAlex Frid
2017-08-23clk: tegra: Re-factor T210 PLLX registrationAlex Frid
2017-08-23clk: tegra: don't warn for pll_d2 defaults unnecessarilyPeter De Schrijver
2017-08-23clk: tegra: Fix T210 effective NDIV calculationAlex Frid
2017-08-23clk: tegra210: remove non-existing VFIR clockPeter De Schrijver
2017-08-23clk: tegra: disable SSC for PLL_D2Peter De Schrijver
2017-04-04clk: tegra: Don't reset PLL-CX if it is already enabledJon Hunter
2017-04-04clk: tegra: Add missing Tegra210 clocksPeter De Schrijver
2017-03-20clk: tegra: Mark TEGRA210_CLK_DBGAPB as always onPeter De Schrijver
2017-03-20clk: tegra: Add SATA seq input controlPeter De Schrijver
2017-03-20clk: tegra: Add Tegra210 special resetsPeter De Schrijver
2017-03-20clk: tegra: Rework pll_uPeter De Schrijver
2017-03-20clk: tegra: Handle UTMIPLL IDDQPeter De Schrijver
2017-03-20clk: tegra: Add aclkPeter De Schrijver
2017-03-20clk: tegra: Define Tegra210 DMIC clocksPeter De Schrijver
2017-03-20clk: tegra: Define Tegra210 DMIC sync clocksPeter De Schrijver
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver
2017-03-20clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculationPeter De Schrijver
2017-03-20clk: tegra: Don't warn for PLL defaults unnecessarilyPeter De Schrijver
2017-03-20clk: tegra: Remove non-existing pll_m_out1 clockPeter De Schrijver
2017-03-20clk: tegra: Fix ISP clock modellingPeter De Schrijver
2017-03-20clk: tegra: Fix pll_a1 iddq register, add pll_a1Peter De Schrijver
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker
2016-06-23clk: tegra: Micro-optimize Tegra210 clock setupThierry Reding
2016-06-23clk: tegra: Make sor_safe the parent of dpaux and dpaux1Thierry Reding
2016-06-17clk: tegra: Enable sor1 and sor1_src on Tegra210Thierry Reding
2016-06-17clk: tegra: Disable spread spectrum on pll_d2Thierry Reding
2016-06-10clk: tegra: Fixup post dividers on Tegra210Thierry Reding
2016-05-27remove lots of IS_ERR_VALUE abusesArnd Bergmann
2016-04-28clk: tegra: Fix pllre Tegra210 and add pll_re_out1Rhyland Klein
2016-04-28clk: tegra: Add sor_safe clockThierry Reding
2016-04-28clk: tegra: dpaux and dpaux1 are fixed factor clocksThierry Reding
2016-04-28clk: tegra: Add dpaux1 clockThierry Reding
2016-04-28clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLsAndrew Bresticker
2016-02-02clk: tegra: Fix sparse warnings for functions not declared as staticJon Hunter
2016-02-02clk: tegra: Fix sparse warning for pll_mJon Hunter
2016-02-02clk: tegra: Use definition for pll_u override bitJon Hunter
2016-02-02clk: tegra: Fix warning caused by pll_u failing to lockJon Hunter
2016-02-02clk: tegra: Fix clock sources for Tegra210 EMCJon Hunter
2016-02-02clk: tegra: Add the APB2APE audio clock on Tegra210Jon Hunter
2016-02-02clk: tegra: Fix pllx dyn step calculationRhyland Klein
2016-02-02clk: tegra: Fix naming of MISC registersRhyland Klein
2016-01-25clk: tegra: Remove improper flags for lock_enableRhyland Klein
2015-12-17clk: tegra: Add support for Tegra210 clocksRhyland Klein