summaryrefslogtreecommitdiff
path: root/drivers/clk
AgeCommit message (Collapse)Author
2017-11-03Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fix from Stephen Boyd: "One fix for USB clks on Uniphier PXs3 SoCs" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: uniphier: fix clock data for PXs3
2017-11-03Update MIPS email addressesPaul Burton
MIPS will soon not be a part of Imagination Technologies, and as such many @imgtec.com email addresses will no longer be valid. This patch updates the addresses for those who: - Have 10 or more patches in mainline authored using an @imgtec.com email address, or any patches dated within the past year. - Are still with Imagination but leaving as part of the MIPS business unit, as determined from an internal email address list. - Haven't already updated their email address (ie. JamesH) or expressed a desire to be excluded (ie. Maciej). - Acked v2 or earlier of this patch, which leaves Deng-Cheng, Matt & myself. New addresses are of the form firstname.lastname@mips.com, and all verified against an internal email address list. An entry is added to .mailmap for each person such that get_maintainer.pl will report the new addresses rather than @imgtec.com addresses which will soon be dead. Instances of the affected addresses throughout the tree are then mechanically replaced with the new @mips.com address. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@mips.com> Acked-by: Dengcheng Zhu <dengcheng.zhu@mips.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Matt Redfearn <matt.redfearn@mips.com> Acked-by: Matt Redfearn <matt.redfearn@mips.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-10-24clk: uniphier: fix clock data for PXs3Masahiro Yamada
Fix reg offsets of USB clocks. Fixes: 736de651a836 ("clk: uniphier: add PXs3 clock data") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-10-04clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycleMarek Szyprowski
Commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks") added enable/disable operations to PLL clocks. Prior that VPLL and EPPL clocks were always enabled because the enable bit was never touched. Those clocks have to be enabled during suspend/resume cycle, because otherwise board fails to enter sleep mode. This patch enables them unconditionally before entering system suspend state. System restore function will set them to the previous state saved in the register cache done before that unconditional enable. Fixes: 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks") CC: stable@vger.kernel.org # v4.13 Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-29Merge tag 'v4.14-rockchip-clkfixes-1' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes Pull Rockchip clk driver fixes from Heiko Stuebner: Some smallish fixes for the rk3128 clock support including some register errors and some clocks that should be critical for safe usage. * tag 'v4.14-rockchip-clkfixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: add sclk_timer5 as critical clock on rk3128 clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs error clk: rockchip: add pclk_pmu as critical clock on rk3128
2017-09-29clk: Export clk_bulk_prepare()Bjorn Andersson
Allow clk_bulk_prepare() to be referenced by kernel modules by adding the missing EXPORT_SYMBOL_GPL(). Fixes: 266e4e9d9150 ("clk: add clk_bulk_get accessories") Reported-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-17clk: rockchip: add sclk_timer5 as critical clock on rk3128Elaine Zhang
sclk_timer5 is for arm arch counter, so need always on. but no dts node to handle this clk, so make it as critical clock Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-09-17clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs errorElaine Zhang
A copy-paste error made them use the wrong bits in the register. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-09-17clk: rockchip: add pclk_pmu as critical clock on rk3128Elaine Zhang
pclk_pmu need always on, and no dts node to handle this clk, so make it as critical clock Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-09-13Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The diff is dominated by the Allwinner A10/A20 SoCs getting converted to the sunxi-ng framework. Otherwise, the heavy hitters are various drivers for SoCs like AT91, Amlogic, Renesas, and Rockchip. There are some other new clk drivers in here too but overall this is just a bunch of clk drivers for various different pieces of hardware and a collection of non-critical fixes for clk drivers. New Drivers: - Allwinner R40 SoCs - Renesas R-Car Gen3 USB 2.0 clock selector PHY - Atmel AT91 audio PLL - Uniphier PXs3 SoCs - ARC HSDK Board PLLs - AXS10X Board PLLs - STMicroelectronics STM32H743 SoCs Removed Drivers: - Non-compiling mb86s7x support Updates: - Allwinner A10/A20 SoCs converted to sunxi-ng framework - Allwinner H3 CPU clk fixes - Renesas R-Car D3 SoC - Renesas V2H and M3-W modules - Samsung Exynos5420/5422/5800 audio fixes - Rockchip fractional clk approximation fixes - Rockchip rk3126 SoC support within the rk3128 driver - Amlogic gxbb CEC32 and sd_emmc clks - Amlogic meson8b reset controller support - IDT VersaClock 5P49V5925/5P49V6901 support - Qualcomm MSM8996 SMMU clks - Various 'const' applications for struct clk_ops - si5351 PLL reset bugfix - Uniphier audio on LD11/LD20 and ethernet support on LD11/LD20/Pro4/PXs2 - Assorted Tegra clk driver fixes" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (120 commits) clk: si5351: fix PLL reset ASoC: atmel-classd: remove aclk clock ASoC: atmel-classd: remove aclk clock from DT binding clk: at91: clk-generated: make gclk determine audio_pll rate clk: at91: clk-generated: create function to find best_diff clk: at91: add audio pll clock drivers dt-bindings: clk: at91: add audio plls to the compatible list clk: at91: clk-generated: remove useless divisor loop clk: mb86s7x: Drop non-building driver clk: ti: check for null return in strrchr to avoid null dereferencing clk: Don't write error code into divider register clk: uniphier: add video input subsystem clock clk: uniphier: add audio system clock clk: stm32h7: Add stm32h743 clock driver clk: gate: expose clk_gate_ops::is_enabled clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled() clk: uniphier: add PXs3 clock data clk: hi6220: change watchdog clock source clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808 clk: cs2000: Add cs2000_set_saved_rate ...
2017-09-10Merge tag 'armsoc-devicetree' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM/arm64 Devicetree updates from Olof Johansson: "As usual, device tree updates is the bulk of our material in this merge window. This time around, 559 patches affecting both 32- and 64-bit platforms. Changes are too many to list individually, but some of the larger ones: New platform/SoC support: - Automotive: + Renesas R-Car D3 (R8A77995) + TI DT76x + MediaTek mt2712e - Communication-oriented: + Qualcomm IPQ8074 + Broadcom Stingray + Marvell Armada 8080 - Set top box: + Uniphier PXs3 Besides some vendor reference boards for the SoC above, there are also several new boards/machines: - TI AM335x Moxa UC-8100-ME-T open platform - TI AM57xx Beaglebone X15 Rev C - Microchip/Atmel sama5d27 SoM1 EK - Broadcom Raspberry Pi Zero W - Gemini-based D-Link DIR-685 router - Freescale i.MX6: + Toradex Apalis module + Apalis and Ixora carrier boards + Engicam GEAM6UL Starter Kit - Freescale i.MX53-based Beckhoff CX9020 Embedded PC - Mediatek mt7623-based BananaPi R2 - Several Allwinner-based single-board computers: + Cubietruck plus + Bananapi M3, M2M and M64 + NanoPi A64 + A64-OLinuXino + Pine64 - Rockchip RK3328 Pine64/Rock64 board support - Rockchip RK3399 boards: + RK3399 Sapphire module on Excavator carrier (RK3399 reference design) + Theobroma Systems RK3399-Q7 SoM - ZTE ZX296718 PCBOX Board" * tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (559 commits) ARM: dts: at91: at91sam9g45: add AC97 arm64: dts: marvell: mcbin: enable more networking ports arm64: dts: marvell: add a reference to the sysctrl syscon in the ppv2 node arm64: dts: marvell: add TX interrupts for PPv2.2 arm64: dts: uniphier: add PXs3 SoC support ARM: dts: uniphier: add pinctrl groups of ethernet phy mode ARM: dts: uniphier: fix size of sdctrl nodes ARM: dts: uniphier: add AIDET nodes arm64: dts: uniphier: fix size of sdctrl node arm64: dts: uniphier: add AIDET nodes Revert "ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Beelink X2" arm64: dts: uniphier: add reset controller node of analog amplifier arm64: dts: marvell: add Device Tree files for Armada-8KP arm64: dts: rockchip: add Haikou baseboard with RK3399-Q7 SoM arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM dt-bindings: add rk3399-q7 SoM ARM: dts: rockchip: enable usb for rv1108-evb ARM: dts: rockchip: add usb nodes for rv1108 SoCs dt-bindings: update grf-binding for rv1108 SoCs ARM: dts: aspeed-g4: fix AHB window size of the SMC controllers ...
2017-09-01clk: si5351: fix PLL resetRussell King
Changing the audio sample rate on the SolidRun Cubox disrupts the video output. The Si5351 provides both the video clock (using PLLA on output 0) and the audio clock (using PLLB on output 2). When the rate of clock output 2 is changed, it reconfigures PLLB, which results in both PLLA and PLLB being reset. The reset of PLLA causes clock output 0 to be disrupted, thereby causing a loss of sync by the attached display device. Hence, each time the audio sample rate changes (eg, when a video player starts up, or when starting to play music) the video display momentarily blanks while the Si5351 settles down. Prior to the commit below, this behaviour did not happen. Fix this by only resetting only the PLL which has been changed. Fixes: 6dc669a22c77 ("clk: si5351: Add PLL soft reset") Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-01clk: at91: clk-generated: make gclk determine audio_pll rateQuentin Schulz
This allows gclk to determine audio_pll rate and set the parent rate accordingly. However, there are multiple children clocks that could technically change the rate of audio_pll (via gck). With the rate locking, the first consumer to enable the clock will be the one definitely setting the rate of the clock. Since audio IPs are most likely to request the same rate, we enforce that the only clks able to modify gck rate are those of audio IPs. To remain consistent, we deny other clocks to be children of audio_pll. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-01clk: at91: clk-generated: create function to find best_diffQuentin Schulz
The way to find the best_diff and do the appropriate process afterwards can be re-used. This patch prepares the driver for an upcoming patch that will allow clk_generated to determine the rate of the audio_pll. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-01clk: at91: add audio pll clock driversQuentin Schulz
This new clock driver set allows to have a fractional divided clock that would generate a precise clock particularly suitable for audio applications. The main audio pll clock has two children clocks: one that is connected to the PMC, the other that can directly drive a pad. As these two routes have different enable bits and different dividers and divider formulas, they are handled by two different drivers. Each of them could modify the rate of the main audio pll parent. The main audio pll clock can output 620MHz to 700MHz. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-01clk: at91: clk-generated: remove useless divisor loopQuentin Schulz
The driver requests the current clk rate of each of its parent clocks to decide whether a clock rate is suitable or not. It does not request determine_rate from a parent clock which could request a rate change in parent clock (i.e. there is no parent rate propagation). We know the rate we want (passed along req argument of the function) and the parent clock rate, thus we know the closest rounded divisor, we don't need to iterate over the available divisors to find the best one for a given clock. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-01clk: mb86s7x: Drop non-building driverAndreas Färber
It fails to build once we introduce the ARCH_MB86S7X Kconfig symbol: drivers/clk/clk-mb86s7x.c:27:10: fatal error: soc/mb86s7x/scb_mhu.h: No such file or directory #include <soc/mb86s7x/scb_mhu.h> ^~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. And when commenting out that line, we get: drivers/clk/clk-mb86s7x.c: In function 'crg_gate_control': drivers/clk/clk-mb86s7x.c:72:8: error: implicit declaration of function 'mb86s7x_send_packet' [-Werror=implicit-function-declaration] ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ, ^~~~~~~~~~~~~~~~~~~ drivers/clk/clk-mb86s7x.c:72:28: error: 'CMD_PERI_CLOCK_GATE_SET_REQ' undeclared (first use in this function) ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ, ^~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/clk-mb86s7x.c:72:28: note: each undeclared identifier is reported only once for each function it appears in drivers/clk/clk-mb86s7x.c: In function 'crg_rate_control': drivers/clk/clk-mb86s7x.c:116:10: error: 'CMD_PERI_CLOCK_RATE_SET_REQ' undeclared (first use in this function) code = CMD_PERI_CLOCK_RATE_SET_REQ; ^~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/clk-mb86s7x.c:121:10: error: 'CMD_PERI_CLOCK_RATE_GET_REQ' undeclared (first use in this function); did you mean 'CMD_PERI_CLOCK_RATE_SET_REQ'? code = CMD_PERI_CLOCK_RATE_GET_REQ; ^~~~~~~~~~~~~~~~~~~~~~~~~~~ CMD_PERI_CLOCK_RATE_SET_REQ drivers/clk/clk-mb86s7x.c: In function 'mhu_cluster_rate': drivers/clk/clk-mb86s7x.c:276:10: error: 'CMD_CPU_CLOCK_RATE_GET_REQ' undeclared (first use in this function) code = CMD_CPU_CLOCK_RATE_GET_REQ; ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/clk-mb86s7x.c:278:10: error: 'CMD_CPU_CLOCK_RATE_SET_REQ' undeclared (first use in this function); did you mean 'CMD_CPU_CLOCK_RATE_GET_REQ'? code = CMD_CPU_CLOCK_RATE_SET_REQ; ^~~~~~~~~~~~~~~~~~~~~~~~~~ CMD_CPU_CLOCK_RATE_GET_REQ cc1: some warnings being treated as errors scripts/Makefile.build:302: recipe for target 'drivers/clk/clk-mb86s7x.o' failed make[2]: *** [drivers/clk/clk-mb86s7x.o] Error 1 Remove the driver for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31clk: ti: check for null return in strrchr to avoid null dereferencingColin Ian King
strrchr can potentially return a null so the following strlen on the null pointer can cause a null dereference. Add a check to see if the string postfix is not null before calling strlen. Detected by CoverityScan, CID#1452039 ("Dereference null return") Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31clk: Don't write error code into divider registerAlex Frid
Add a check for error returned by divider value calculation to avoid writing error code into hw register. Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Fixes: bca9690b9426 ("clk: divider: Make generic for usage elsewhere") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31clk: uniphier: add video input subsystem clockKatsuhiro Suzuki
Add a clock for video input subsystem (EXIV) on UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31clk: uniphier: add audio system clockKatsuhiro Suzuki
Add clock for audio subsystem (AIO) and SoC internal audio codec (EVEA) on UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31clk: stm32h7: Add stm32h743 clock driverGabriel Fernandez
This patch enables clocks for STM32H743 boards. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> for MFD changes: Acked-by: Lee Jones <lee.jones@linaro.org> for DT-Bindings Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31clk: gate: expose clk_gate_ops::is_enabledGabriel Fernandez
This patch exposes clk_gate_ops::is_enabled as functions that can be directly called and assigned in places like this so we don't need wrapper functions that do nothing besides forward the call. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Suggested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled()Gabriel Fernandez
We need to export clk_gate_is_enabled() from clk framework, then to avoid compilation issue we have to rename clk_gate_is_enabled() in NXP LPC32xx clock driver. We changed all gate op with 'lpc32xx_' prefix: lpc32xx_clk_gate_enable(), lpc32xx_clk_gate_disable(), lpc32xx_clk_gate_is_enabled(). Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31clk: uniphier: add PXs3 clock dataMasahiro Yamada
Add basic clock data for Socionext's new SoC PXs3. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31clk: hi6220: change watchdog clock sourceLeo Yan
The old code uses tcxo (19.2MHz) as watchdog clock but actually the watchdog uses 32K clock, as result the watchdog timeout cannot be set correctly and delay long time to reset SoC. So this patch is to use 'ref32k' as clock source for watchdog. Fixes: 72ea48610d43 ("clk: hi6220: Clock driver support for Hisilicon hi6220 SoC") Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808Elaine Zhang
The RK808 and RK805 PMICs are using a similar register map. We can reuse the clk driver for the RK805 PMIC. So let's add the RK805 in the Kconfig description. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31clk: cs2000: Add cs2000_set_saved_rateGaku Inami
This patch adds the common function to reset the clk rate in order to be able to use it in other cases. Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31clk: imx51: propagate rate across ipu_di*_selLucas Stach
This propagates rate requests from the display interface to the divider or PLL output, allowing to hit the required display rate in many more cases. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-By: Wladimir J. van der Laan <laanwj@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31Merge tag 'sunxi-clk-for-4.14-3' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next Pull more Allwinner clock changes from Maxime Ripard: * Conversion of the last two SoCs (A10, A20) to the sunxi-ng framework * tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: Add sun4i/sun7i CCU driver dt-bindings: List devicetree binding for the CCU of Allwinner A10 dt-bindings: List devicetree binding for the CCU of Allwinner A20
2017-08-30clk: sunxi: fix uninitialized accessArnd Bergmann
gcc-8 reports an uninitialized variable access in a code path that we would see with incorrect DTB input: drivers/clk/sunxi/clk-sun8i-bus-gates.c: In function 'sun8i_h3_bus_gates_init': drivers/clk/sunxi/clk-sun8i-bus-gates.c:85:27: error: 'clk_parent' may be used uninitialized in this function [-Werror=maybe-uninitialized] This works around by skipping invalid input and printing a warning instead if it ever happens. The problem was apparently part of the initiali driver submission, but older compilers don't notice it. Fixes: ab6e23a4e388 ("clk: sunxi: Add H3 clocks support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-30clk: versatile: make clk_ops constBhumika Goyal
Make this const as it is only stored in the const field of a clk_init_data structure. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-30ARC: clk: introduce HSDK pll driverEugeniy Paltsev
HSDK board manages its clocks using various PLLs. These PLL have same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the HSDK arc cpus, system, ddr, AXI tunnel and hdmi. By this patch we add support for several plls (arc cpus pll and others), so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll and regular probing for others plls. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-30clk: zte: constify clk_div_tableArvind Yadav
clk_div_table are not supposed to change at runtime. All functions working with clk_div_table provided by <linux/clk-provider.h> work with const clk_div_table. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-30clk: imx: constify clk_div_tableArvind Yadav
clk_div_table are not supposed to change at runtime. All functions working with clk_div_table provided by <linux/clk-provider.h> work with const clk_div_table. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-30clk: uniphier: add ethernet clock control supportKunihiko Hayashi
Add clock control for ethernet controller on Pro4, PXs2, LD11 and LD20. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-30clk: gemini: hands off PCI OE bitLinus Walleij
This bit is pin control, and needs to be carefully managed by the new pin control driver. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-30clk: ux500: prcc: constify clk_ops.Arvind Yadav
clk_ops are not supposed to change at runtime. All functions working with clk_ops provided by <linux/clk-provider.h> work with const clk_ops. So mark the non-const clk_ops as const. Here, Function "clk_reg_prcc" is used to initialized clk_init_data. clk_init_data is working with const clk_ops. So make clk_reg_prcc non-const clk_ops argument as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-30clk: ux500: sysctrl: constify clk_ops.Arvind Yadav
clk_ops are not supposed to change at runtime. All functions working with clk_ops provided by <linux/clk-provider.h> work with const clk_ops. So mark the non-const clk_ops as const. Here, Function "clk_reg_sysctrl" is used to initialized clk_init_data. clk_init_data is working with const clk_ops. So make clk_reg_sysctrl non-const clk_ops argument as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-30clk: ux500: prcmu: constify clk_ops.Arvind Yadav
clk_ops are not supposed to change at runtime. All functions working with clk_ops provided by <linux/clk-provider.h> work with const clk_ops. So mark the non-const clk_ops as const. Here, Function "clk_reg_prcmu" is used to initialized clk_init_data. clk_init_data is working with const clk_ops. So make clk_reg_prcmu non-const clk_ops argument as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-30clk: sunxi-ng: Provide a default reset hookMaxime Ripard
The reset hook was left implemented. Provide a dumb implementation so that client drivers can depend on it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30clk: sunxi-ng: a83t: Support new timing mode for mmc2 clockChen-Yu Tsai
The MMC2 clock supports a new timing mode. When the new mode is active, the output clock rate is halved. This patch sets the feature flag for the new timing mode, and adds a pre-divider based on the mode bit. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30clk: sunxi-ng: Add MP_MMC clocks that support MMC timing modes switchingChen-Yu Tsai
All of our MMC clocks are of the MP clock type. A few MMC clocks on some SoCs, such as MMC2 on the A83T, support new/old timing mode switching. >From a clock rate point of view, when the new timing mode is active. the output clock rate is halved. This patch adds a special wrapper class of clocks, MP_MMC, around the generic MP type clocks. The rate related callbacks in ccu_mp_mmc_ops for this class look at the timing mode bit and apply the /2 post-divider when needed, before passing it through to the generic class ops, ccu_mp_ops. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30clk: sunxi-ng: Add interface to query or configure MMC timing modes.Chen-Yu Tsai
Starting with the A83T SoC, Allwinner introduced a new timing mode for its MMC clocks. The new mode changes how the MMC controller sample and output clocks are delayed to match chip and board specifics. There are two controls for this, one on the CCU side controlling how the clocks behave, and one in the MMC controller controlling what inputs to take and how to route them. In the old mode, the MMC clock had 2 child clocks providing the output and sample clocks, which could be delayed by a number of clock cycles measured from the MMC clock's parent. With the new mode, the 2 delay clocks are no longer active. Instead, the delays and associated controls are moved into the MMC controller. The output of the MMC clock is also halved. The difference in how things are wired between the modes means that the clock controls and the MMC controls must match. To achieve this in a clear, explicit way, we introduce two functions for the MMC driver to use: one queries the hardware for the current mode set, and the other allows the MMC driver to request a mode. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-24clk: sunxi-ng: Add sun4i/sun7i CCU driverPriit Laes
Introduce a clock controller driver for sun4i A10 and sun7i A20 series SoCs. Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-08-23clk: msm8996-gcc: add missing smmu clksSrinivas Kandagatla
This patch adds missing LPASS smmu clks which are required by the audio driver. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-23clk: tegra: Fix Tegra210 PLLU initializationAlex Frid
- Added necessary delays in PLLU enable sequence during initialization - Applied PLLU lock to all secondary gates (PLLU_48M and PLLU_60M were missing). Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-23clk: tegra: Correct Tegra210 UTMIPLL poweron delayAlex Frid
Increased Tegra210 UTMIPLL power on delay to 20us (spec maximum is 15us). Also remove a few empty lines to make it more clear the ACTIVE_DLY_COUNT and ENABLE_DLY_COUNT fields. Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-23clk: tegra: Fix T210 PLLRE registrationAlex Frid
Switched Tegra210 PLLRE registration to common PLL ops instead of special PLLRE ops used on previous Tegra chips. The latter ops do not follow chip specific PLL frequency table, and do not apply chip specific rate calculation method. Removed unnecessary default rate setting that duplicates h/w reset state, and is overwritten by clock initialization, anyway. Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>